arXiv subjects

Pranav S. Mundada

Publications and source records attributed to Pranav S. Mundada.

14 recordsLinked to original sources

arXiv2026

Driving Exchange Interaction in Spin Qubits with Quasi-Zero Pulses

The implementation of high-fidelity quantum gates for spin qubits requires accurate control of exchange interactions between electrons confined in quantum dots, but pulse distortions can limit this control accuracy. Although linear-dynamical distortions can be compensated for by appropriately convolving the control signal, determining the necessary convolution requires detailed knowledge of the distortion's transfer function, and therefore the calibration of numerous parameters. Alternatively, control pulses can be designed to have a net-zero time integral canceling out linear-dynamical pulse distortions. We generalize net-zero pulse designs to quasi-zero pulses allowing net-positive but reduced time integrals. Using these pulse designs, we systematically develop complete gate sets for exchange-only qubits, and study the resulting tradeoffs between pulse duration, fidelity, and the required number of tunable parameters, both in simulation and experiment. We benchmark the optimized gate pulses on Intel's Tunnel Falls six-dot device and show they achieve fidelities similar to those obtained with a full filtering approach, with identical pulse durations and fewer tuning parameters. This reduction in complexity opens the door to fast and easily automated calibration schemes compatible with large-scale commercial quantum devices.

quant-ph↗

arXiv2026

Heterogeneous architectures enable a 138x reduction in physical qubit requirements for fault-tolerant quantum computing under detailed accounting

Quantum computer hardware is predicted to scale over hundreds of thousands of qubits coming online in the next decade. Despite significant theoretical and experimental QEC progress, quantum computer architecture has suffered a significant gap, with bottom-up physical-device-driven challenges largely disconnected from top-down QEC-code-driven considerations. In this work, we unify these two views, presenting a complete heterogeneous quantum computing architecture incorporating task-specific hardware selection and QEC encoding, and agnostic to code selection or physical qubit parameters. Our approach further enables special-purpose processing modules, and includes a full microarchitecture for fault-tolerant implementation of interfaces between quantum processing units and quantum memories. Using this architecture and a new fully featured compiler functioning across subsystems at the scale of $1,000$ logical qubits, we schedule and orchestrate a variety of algorithms down to hardware-specific instructions; a detailed accounting of all operations reveals up to 551x reduction in algorithmic logical error and up to 138x reduction in physical-qubit overhead compared to a monolithic baseline architecture. We then consider the factorization of 2048-bit RSA-integers; using an experimentally demonstrated grid-coupling topology, factoring RSA-2048 requires 381k physical qubits and 9.2 days, which can be reduced to 4.9 days via addition of an algorithm-specific accelerator for the Adder subroutine (requiring 439k qubits). Finally, assuming hypothetical long-range coupling, implementing quantum memory using qLDPC codes reduces the resources required for factoring to just 190k qubits and under 10 days. These results and the tooling we have built indicate that heterogeneous quantum-computer architectures can deliver significant, verifiable benefits on realistic hardware.

quant-ph↗

arXiv2026

Automated discovery of heralded ballistic graph state generators for fusion-based photonic quantum computation

Designing photonic circuits that prepare graph states with high fidelity and success probability is a central challenge in linear optical quantum computing. Existing approaches rely on hand-crafted designs or fusion-based assemblies. In the absence of multiplexing/boosting, both post-selected ballistic circuits and sequential fusion exhibit exponentially decreasing single-shot yields - a fundamental limitation that makes optimizing individual resource state generators particularly important, as these serve as building blocks in larger FBQC architectures. We present a general-purpose optimization framework for automated photonic circuit discovery using a novel polynomial-based simulation approach, enabling efficient strong simulation and gradient-based optimization. Our framework employs a two-pass optimization procedure: the first pass identifies a unitary transformation that prepares the desired state with perfect fidelity and maximal success probability, and the second pass implements a novel sparsification algorithm that reduces this solution to a compact photonic circuit with minimal beamsplitter count while preserving performance. This sparsification procedure often reveals underlying mathematical structure, producing highly simplified circuits with rational reflection coefficients. We demonstrate our approach by discovering optimized circuits for $3$-, $4$-, and $5$-qubit graph states across multiple equivalence classes. For 4-qubit states, our circuits achieve success probabilities of $2.053 \times 10^{-3}$ to $7.813 \times 10^{-3}$, outperforming the fusion baseline by up to $4.7 \times$. For 5-qubit states, we achieve $5.926 \times 10^{-5}$ to $1.157 \times 10^{-3}$, demonstrating up to $7.5 \times$ improvement. These results include the first known state preparation circuits for certain 5-qubit graph states.

quant-ph↗

arXiv2026

Integrated error-suppressed pipeline for quantum optimization of nontrivial binary combinatorial optimization problems on gate-model hardware at the 156-qubit scale

We introduce a novel hybrid quantum-classical variational optimization method for unconstrained binary combinatorial optimization problems on gate-model quantum computers, integrating a custom variational ansatz, staged feedback-based dual variational parameter update strategies, efficient parametric compilation, automated error suppression during hardware execution, and scalable O($n$) classical post-processing to correct for bitflip errors. Without this integrated approach, we show that standard circuit execution at scale produces output indistinguishable from random sampling, establishing the necessity of each pipeline component. We benchmark the method on IBM superconducting quantum computers for classically nontrivial optimization problems, where the optimization is conducted on hardware with no use of classical simulation or prior knowledge of the solution. For Max-Cut on random regular graphs with topologies not matched to device connectivity, the method achieves approximation ratios of 100% for unweighted 3-regular graphs up to 156 nodes, weighted regular graphs up to 80 nodes, and weighted 7-regular graphs up 50 nodes. Applied to higher-order binary optimization, the method finds the ground state energy of 127- and 156-qubit spin-glass models matched to device topology with linear, quadratic, and cubic interaction terms, achieving approximation ratios of at least 99.5% across all instances tested. The method consistently outperforms a classical local solver across all problems. Where published results on identical problem instances are available, our method demonstrates competitive or superior performance. These results demonstrate that an appropriately engineered approach enables gate-model quantum computers to produce high-quality solutions for nontrivial binary optimization problems at the 156 qubit scale, where naive implementations are insufficient for good performance.

quant-ph↗

arXiv2025

Achieving computational gains with quantum error-correction primitives: Generation of long-range entanglement enhanced by error detection

The resource overhead required to achieve net computational benefits from quantum error correction (QEC) limits its utility while current systems remain constrained in size, despite exceptional progress in experimental demonstrations. In this paper, we demonstrate that the strategic application of QEC primitives without logical encoding can yield significant advantages on superconducting processors--relative to any alternative error-reduction strategy--while only requiring a modest overhead. We first present a novel protocol for implementing long-range CNOT gates that relies on a unitarily prepared Greenberger-Horne-Zeilinger (GHZ) state as well as a unitary disentangling step; the protocol natively introduces an error-detection process using the disentangled qubits as flags. We demonstrate that it achieves state-of-the-art gate fidelities of over 85% across up to 40 lattice sites, significantly and consistently outperforming the best alternative measurement-based protocol without introducing any additional ancilla qubits. We then apply sparse stabilizer measurements to generate large GHZ states by detecting bit-flip and amplitude-damping errors. Employing this technique in combination with deterministic error suppression, we generate a 75-qubit GHZ state exhibiting genuine multipartite entanglement, the largest reported to date. The generation requires no more than 9 ancilla qubits and the fraction of samples discarded due to errors grows no higher than 78%, far lower than previous discard fractions required for tests using comparable numbers of fully encoded qubits. This work in total represents compelling evidence that adopting QEC primitives on current-generation devices can deliver substantial net benefits.

quant-ph↗

arXiv2024

Learning to rank quantum circuits for hardware-optimized performance enhancement

We introduce and experimentally test a machine-learning-based method for ranking logically equivalent quantum circuits based on expected performance estimates derived from a training procedure conducted on real hardware. We apply our method to the problem of layout selection, in which abstracted qubits are assigned to physical qubits on a given device. Circuit measurements performed on IBM hardware indicate that the maximum and median fidelities of logically equivalent layouts can differ by an order of magnitude. We introduce a circuit score used for ranking that is parameterized in terms of a physics-based, phenomenological error model whose parameters are fit by training a ranking-loss function over a measured dataset. The dataset consists of quantum circuits exhibiting a diversity of structures and executed on IBM hardware, allowing the model to incorporate the contextual nature of real device noise and errors without the need to perform an exponentially costly tomographic protocol. We perform model training and execution on the 16-qubit ibmq_guadalupe device and compare our method to two common approaches: random layout selection and a publicly available baseline called Mapomatic. Our model consistently outperforms both approaches, predicting layouts that exhibit lower noise and higher performance. In particular, we find that our best model leads to a $1.8\times$ reduction in selection error when compared to the baseline approach and a $3.2\times$ reduction when compared to random selection. Beyond delivering a new form of predictive quantum characterization, verification, and validation, our results reveal the specific way in which context-dependent and coherent gate errors appear to dominate the divergence from performance estimates extrapolated from simple proxy measures.

quant-ph↗

arXiv2024

Data needs and challenges for quantum dot devices automation

Gate-defined quantum dots are a promising candidate system for realizing scalable, coupled qubit systems and serving as a fundamental building block for quantum computers. However, present-day quantum dot devices suffer from imperfections that must be accounted for, which hinders the characterization, tuning, and operation process. Moreover, with an increasing number of quantum dot qubits, the relevant parameter space grows sufficiently to make heuristic control infeasible. Thus, it is imperative that reliable and scalable autonomous tuning approaches are developed. This meeting report outlines current challenges in automating quantum dot device tuning and operation with a particular focus on datasets, benchmarking, and standardization. We also present insights and ideas put forward by the quantum dot community on how to overcome them. We aim to provide guidance and inspiration to researchers invested in automation efforts.

cond-mat.mes-hall↗

arXiv2024

Quantum Algorithm Exploration using Application-Oriented Performance Benchmarks

The QED-C suite of Application-Oriented Benchmarks provides the ability to gauge performance characteristics of quantum computers as applied to real-world applications. Its benchmark programs sweep over a range of problem sizes and inputs, capturing key performance metrics related to the quality of results, total time of execution, and quantum gate resources consumed. In this manuscript, we investigate challenges in broadening the relevance of this benchmarking methodology to applications of greater complexity. First, we introduce a method for improving landscape coverage by varying algorithm parameters systematically, exemplifying this functionality in a new scalable HHL linear equation solver benchmark. Second, we add a VQE implementation of a Hydrogen Lattice simulation to the QED-C suite, and introduce a methodology for analyzing the result quality and run-time cost trade-off. We observe a decrease in accuracy with increased number of qubits, but only a mild increase in the execution time. Third, unique characteristics of a supervised machine-learning classification application are explored as a benchmark to gauge the extensibility of the framework to new classes of application. Applying this to a binary classification problem revealed the increase in training time required for larger anzatz circuits, and the significant classical overhead. Fourth, we add methods to include optimization and error mitigation in the benchmarking workflow which allows us to: identify a favourable trade off between approximate gate synthesis and gate noise; observe the benefits of measurement error mitigation and a form of deterministic error mitigation algorithm; and to contrast the improvement with the resulting time overhead. Looking ahead, we discuss how the benchmark framework can be instrumental in facilitating the exploration of algorithmic options and their impact on performance.

quant-ph↗

arXiv2023

Experimental benchmarking of an automated deterministic error suppression workflow for quantum algorithms

Excitement about the promise of quantum computers is tempered by the reality that the hardware remains exceptionally fragile and error-prone, forming a bottleneck in the development of novel applications. In this manuscript, we describe and experimentally test a fully autonomous workflow designed to deterministically suppress errors in quantum algorithms from the gate level through to circuit execution and measurement. We introduce the key elements of this workflow, delivered as a software package called Fire Opal, and survey the underlying physical concepts: error-aware compilation, automated system-wide gate optimization, automated dynamical decoupling embedding for circuit-level error cancellation, and calibration-efficient measurement-error mitigation. We then present a comprehensive suite of performance benchmarks executed on IBM hardware, demonstrating up to > 1000X improvement over the best alternative expert-configured techniques available in the open literature. Benchmarking includes experiments using up to 16 qubit systems executing: Bernstein Vazirani, Quantum Fourier Transform, Grover's Search, QAOA, VQE, Syndrome extraction on a five-qubit Quantum Error Correction code, and Quantum Volume. Experiments reveal a strong contribution of Non-Markovian errors to baseline algorithmic performance; in all cases the deterministic error-suppression workflow delivers the highest performance and approaches incoherent error bounds without the need for any additional sampling or randomization overhead, while maintaining compatibility with all additional probabilistic error suppression techniques.

quant-ph↗

arXiv2022

Let Each Quantum Bit Choose Its Basis Gates

Near-term quantum computers are primarily limited by errors in quantum operations (or gates) between two quantum bits (or qubits). A physical machine typically provides a set of basis gates that include primitive 2-qubit (2Q) and 1-qubit (1Q) gates that can be implemented in a given technology. 2Q entangling gates, coupled with some 1Q gates, allow for universal quantum computation. In superconducting technologies, the current state of the art is to implement the same 2Q gate between every pair of qubits (typically an XX- or XY-type gate). This strict hardware uniformity requirement for 2Q gates in a large quantum computer has made scaling up a time and resource-intensive endeavor in the lab. We propose a radical idea -- allow the 2Q basis gate(s) to differ between every pair of qubits, selecting the best entangling gates that can be calibrated between given pairs of qubits. This work aims to give quantum scientists the ability to run meaningful algorithms with qubit systems that are not perfectly uniform. Scientists will also be able to use a much broader variety of novel 2Q gates for quantum computing. We develop a theoretical framework for identifying good 2Q basis gates on "nonstandard" Cartan trajectories that deviate from "standard" trajectories like XX. We then introduce practical methods for calibration and compilation with nonstandard 2Q gates, and discuss possible ways to improve the compilation. To demonstrate our methods in a case study, we simulated both standard XY-type trajectories and faster, nonstandard trajectories using an entangling gate architecture with far-detuned transmon qubits. We identify efficient 2Q basis gates on these nonstandard trajectories and use them to compile a number of standard benchmark circuits such as QFT and QAOA. Our results demonstrate an 8x improvement over the baseline 2Q gates with respect to speed and coherence-limited gate fidelity.

quant-ph↗

arXiv2020

Engineering Dynamical Sweet Spots to Protect Qubits from 1/$f$ Noise

Protecting superconducting qubits from low-frequency noise is essential for advancing superconducting quantum computation. Based on the application of a periodic drive field, we develop a protocol for engineering dynamical sweet spots which reduce the susceptibility of a qubit to low-frequency noise. Using the framework of Floquet theory, we prove rigorously that there are manifolds of dynamical sweet spots marked by extrema in the quasi-energy differences of the driven qubit. In particular, for the example of fluxonium biased slightly away from half a flux quantum, we predict an enhancement of pure-dephasing by three orders of magnitude. Employing the Floquet eigenstates as the computational basis, we show that high-fidelity single- and two-qubit gates can be implemented while maintaining dynamical sweet-spot operation. We further confirm that qubit readout can be performed by adiabatically mapping the Floquet states back to the static qubit states, and subsequently applying standard measurement techniques. Our work provides an intuitive tool to encode quantum information in robust, time-dependent states, and may be extended to alternative architectures for quantum information processing.

quant-ph↗

arXiv2020

Floquet-engineered enhancement of coherence times in a driven fluxonium qubit

We use the quasienergy structure that emerges when a fluxonium superconducting circuit is driven periodically to encode quantum information with dynamically induced flux-insensitive sweet spots. The framework of Floquet theory provides an intuitive description of these high-coherence working points located away from the half-flux symmetry point of the undriven qubit. This approach offers flexibility in choosing the flux bias point and the energy of the logical qubit states as shown in [\textit{Huang et al., 2020}]. We characterize the response of the system to noise in the modulation amplitude and DC flux bias, and experimentally demonstrate an optimal working point which is simultaneously insensitive against fluctuations in both. We observe a 40-fold enhancement of the qubit coherence times measured with Ramsey-type interferometry at the dynamical sweet spot compared with static operation at the same bias point.

quant-ph↗

arXiv2019

Experimental realization of an intrinsically error-protected superconducting qubit

Encoding a qubit in logical quantum states with wavefunctions characterized by disjoint support and robust energies can offer simultaneous protection against relaxation and pure dephasing. Using a circuit-quantum-electrodynamics architecture, we experimentally realize a superconducting $0-π$ qubit, which hosts protected states suitable for quantum-information processing. Multi-tone spectroscopy measurements reveal the energy level structure of the system, which can be precisely described by a simple two-mode Hamiltonian. We find that the parity symmetry of the qubit results in charge-insensitive levels connecting the protected states, allowing for logical operations. The measured relaxation (1.6 ms) and dephasing times (25 $μ$s) demonstrate that our implementation of the $0-π$ circuit not only broadens the family of superconducting qubits, but also represents a promising candidate for the building block of a fault-tolerant quantum processor.

quant-ph↗

arXiv2019

Suppression of Qubit Crosstalk in a Tunable Coupling Superconducting Circuit

Parasitic crosstalk in superconducting quantum devices is a leading limitation for quantum gates. We demonstrate the suppression of static ZZ crosstalk in a two-qubit, two-coupler superconducting circuit, where the frequency of a tunable coupler can be adjusted such that the ZZ interaction from each coupler destructively interfere. We verify the crosstalk elimination with simultaneous randomized benchmarking, and use a parametrically activated iSWAP interaction to achieve a Bell state preparation fidelity of 98.5% and a $\sqrt{\textrm{iSWAP}}$ gate fidelity of 94.8% obtained via quantum process tomography.

quant-ph↗