arXiv subjects

Qijun Zhang

Publications and source records attributed to Qijun Zhang.

27 records · Page 2Linked to original sources

arXiv2025

A polychromatic continuous-variable quantum communication network enabled by optical frequency combs

In classical communication, the introduction of polychromatic resources has rapidly boosted classical networks' rate and scale. Quantum communication is now at a similar critical stage in its development, and therefore, it is essential to investigate polychromatic quantum communication networks. In this letter, we report a polychromatic continuous-variable quantum communication network enabled by optical frequency combs. The multi-mode density matrices constituted by polychromatic quantum networks are studied. Considering the limited mode isolation, the maximum amount of information that eavesdroppers can obtain is recalculated, therefore, the total secret key rate is provided. We have also demonstrated that, compared to other multiplexing techniques, polychromatic quantum networks can theoretically achieve a secret key rate without decreasing with the increase in users. In the experiment, direct-transmission type and round-trip type quantum communication networks were built using optical frequency combs and dual-comb interference detection technology. The Gaussian-modulated continuous-variable quantum key distribution (CV-QKD) protocol has been validated, with a network capacity of 19 and a total secret key rate of 8.75 Gbps at a uniform distance of 5 km (asymptotic case), 0.82 Mbps at 120 km (finite-size effect), 89.10 Mbps at 40 km (compsable security), 13.66 Mbps at 40 km (compsable finite-size security). This implementation not only provides technical support for a high-speed multi-node quantum network, but also provides a solution for the future quantum Internet with continuous variables.

quant-ph↗

arXiv2025

High-rate self-referenced continuous-variable quantum key distribution over high-loss free-space channel

The advent of quantum computers has significantly challenged the security of traditional cryptographic systems, prompting a surge in research on quantum key distribution (QKD). Among various QKD approaches, continuous-variable QKD (CVQKD) offers superior resilience against background noise. However, the local local oscillator (LLO) CVQKD scheme faces substantial physical limitations in scenarios with high channel attenuation, and the large attenuation CVQKD remains unrealized. Bottleneck challenges include ensuring stable low-noise transmission and accurately estimating parameters under fluctuating channel conditions. In this paper, we introduce a continuous-time mode theory for high-precision estimation of time-varying parameters and design a free-space experimental system with a main quantum system and an auxiliary counterpart. We further develop advanced digital signal post-processing techniques for compensating time-varying frequency offset and phase noise under dynamic channel. Notably, the estimation of the time-varying free-space channel is achieved through the use of the auxiliary quantum system. Through experimental validation, we first demonstrate high-rate secure quantum key distribution over high-loss free-space channels. Specifically, we achieve asymptotic key rates of 76.366 kbps and 403.896 kbps in 25 dB attenuation free-space channels without turbulence and 21.5 dB average attenuation free-space channels with turbulence, respectively. Additionally, we confirm the feasibility of experiments on mildly turbulent atmospheric channels spanning at least 10.5 km using current equipments. Our scheme provides direct insight into constructing an integrated air-ground quantum communication network.

quant-ph↗

arXiv2025

Integrating Prefetcher Selection with Dynamic Request Allocation Improves Prefetching Efficiency

Hardware prefetching plays a critical role in hiding the off-chip DRAM latency. The complexity of applications results in a wide variety of memory access patterns, prompting the development of numerous cache-prefetching algorithms. Consequently, commercial processors often employ a hybrid of these algorithms to enhance the overall prefetching performance. Nonetheless, since these prefetchers share hardware resources, conflicts arising from competing prefetching requests can negate the benefits of hardware prefetching. Under such circumstances, several prefetcher selection algorithms have been proposed to mitigate conflicts between prefetchers. However, these prior solutions suffer from two limitations. First, the input demand request allocation is inaccurate. Second, the prefetcher selection criteria are coarse-grained. In this paper, we address both limitations by introducing an efficient and widely applicable prefetcher selection algorithm--Alecto, which tailors the demand requests for each prefetcher. Every demand request is first sent to Alecto to identify suitable prefetchers before being routed to prefetchers for training and prefetching. Our analysis shows that Alecto is adept at not only harmonizing prefetching accuracy, coverage, and timeliness but also significantly enhancing the utilization of the prefetcher table, which is vital for temporal prefetching. Alecto outperforms the state-of-the-art RL-based prefetcher selection algorithm--Bandit by 2.76% in single-core, and 7.56% in eight-core. For memory-intensive benchmarks, Alecto outperforms Bandit by 5.25%. Alecto consistently delivers state-of-the-art performance in scheduling various types of cache prefetchers. In addition to the performance improvement, Alecto can reduce the energy consumption associated with accessing the prefetchers' table by 48%, while only adding less than 1 KB of storage overhead.

cs.AR↗

arXiv2024

Pointer: An Energy-Efficient ReRAM-based Point Cloud Recognition Accelerator with Inter-layer and Intra-layer Optimizations

Point cloud is an important data structure for a wide range of applications, including robotics, AR/VR, and autonomous driving. To process the point cloud, many deep-learning-based point cloud recognition algorithms have been proposed. However, to meet the requirement of applications like autonomous driving, the algorithm must be fast enough, rendering accelerators necessary at the inference stage. But existing point cloud accelerators are still inefficient due to two challenges. First, the multi-layer perceptron (MLP) during feature computation is the performance bottleneck. Second, the feature vector fetching operation incurs heavy DRAM access. In this paper, we propose Pointer, an efficient Resistive Random Access Memory (ReRAM)-based point cloud recognition accelerator with inter- and intra-layer optimizations. It proposes three techniques for point cloud acceleration. First, Pointer adopts ReRAM-based architecture to significantly accelerate the MLP in feature computation. Second, to reduce DRAM access, Pointer proposes inter-layer coordination. It schedules the next layer to fetch the results of the previous layer as soon as they are available, which allows on-chip fetching thus reduces DRAM access. Third, Pointer proposes topology-aware intra-layer reordering, which improves the execution order for better data locality. Pointer proves to achieve 40x to 393x speedup and 22x to 163x energy efficiency over prior accelerators without any accuracy loss.

cs.AR↗

arXiv2024

FirePower: Towards a Foundation with Generalizable Knowledge for Architecture-Level Power Modeling

Power efficiency is a critical design objective in modern processor design. A high-fidelity architecture-level power modeling method is greatly needed by CPU architects for guiding early optimizations. However, traditional architecture-level power models can not meet the accuracy requirement, largely due to the discrepancy between the power model and actual design implementation. While some machine learning (ML)-based architecture-level power modeling methods have been proposed in recent years, the data-hungry ML model training process requires sufficient similar known designs, which are unrealistic in many development scenarios. This work proposes a new power modeling solution FirePower that targets few-shot learning scenario for new target architectures. FirePower proposes multiple new policies to utilize cross-architecture knowledge. First, it develops power models at component level, and components are defined in a power-friendly manner. Second, it supports different generalization strategies for models of different components. Third, it formulates generalizable and architecture-specific design knowledge into two separate models. FirePower also supports the evaluation of the generalization quality. In our experiments, FirePower can achieve a low error percentage of 5.8% and a high correlation R of 0.98 on average only using two configurations of target architecture. This is 8.8% lower in error percentage and 0.03 higher in R compared with directly training McPAT-Calib baseline on configurations of target architecture.

cs.AR↗

arXiv2024

SpecLLM: Exploring Generation and Review of VLSI Design Specification with Large Language Model

The development of architecture specifications is an initial and fundamental stage of the integrated circuit (IC) design process. Traditionally, architecture specifications are crafted by experienced chip architects, a process that is not only time-consuming but also error-prone. Mistakes in these specifications may significantly affect subsequent stages of chip design. Despite the presence of advanced electronic design automation (EDA) tools, effective solutions to these specification-related challenges remain scarce. Since writing architecture specifications is naturally a natural language processing (NLP) task, this paper pioneers the automation of architecture specification development with the advanced capabilities of large language models (LLMs). Leveraging our definition and dataset, we explore the application of LLMs in two key aspects of architecture specification development: (1) Generating architecture specifications, which includes both writing specifications from scratch and converting RTL code into detailed specifications. (2) Reviewing existing architecture specifications. We got promising results indicating that LLMs may revolutionize how these critical specification documents are developed in IC design nowadays. By reducing the effort required, LLMs open up new possibilities for efficiency and accuracy in this crucial aspect of chip design.

cs.AR↗

arXiv2023

PANDA: Architecture-Level Power Evaluation by Unifying Analytical and Machine Learning Solutions

Power efficiency is a critical design objective in modern microprocessor design. To evaluate the impact of architectural-level design decisions, an accurate yet efficient architecture-level power model is desired. However, widely adopted data-independent analytical power models like McPAT and Wattch have been criticized for their unreliable accuracy. While some machine learning (ML) methods have been proposed for architecture-level power modeling, they rely on sufficient known designs for training and perform poorly when the number of available designs is limited, which is typically the case in realistic scenarios. In this work, we derive a general formulation that unifies existing architecture-level power models. Based on the formulation, we propose PANDA, an innovative architecture-level solution that combines the advantages of analytical and ML power models. It achieves unprecedented high accuracy on unknown new designs even when there are very limited designs for training, which is a common challenge in practice. Besides being an excellent power model, it can predict area, performance, and energy accurately. PANDA further supports power prediction for unknown new technology nodes. In our experiments, besides validating the superior performance and the wide range of functionalities of PANDA, we also propose an application scenario, where PANDA proves to identify high-performance design configurations given a power constraint.

cs.LG↗

arXiv2023

MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design

In modern VLSI design flow, the register-transfer level (RTL) stage is a critical point, where designers define precise design behavior with hardware description languages (HDLs) like Verilog. Since the RTL design is in the format of HDL code, the standard way to evaluate its quality requires time-consuming subsequent synthesis steps with EDA tools. This time-consuming process significantly impedes design optimization at the early RTL stage. Despite the emergence of some recent ML-based solutions, they fail to maintain high accuracy for any given RTL design. In this work, we propose an innovative pre-synthesis PPA estimation framework named MasterRTL. It first converts the HDL code to a new bit-level design representation named the simple operator graph (SOG). By only adopting single-bit simple operators, this SOG proves to be a general representation that unifies different design types and styles. The SOG is also more similar to the target gate-level netlist, reducing the gap between RTL representation and netlist. In addition to the new SOG representation, MasterRTL proposes new ML methods for the RTL-stage modeling of timing, power, and area separately. Compared with state-of-the-art solutions, the experiment on a comprehensive dataset with 90 different designs shows accuracy improvement by 0.33, 0.22, and 0.15 in correlation for total negative slack (TNS), worst negative slack (WNS), and power, respectively.

cs.AR↗

arXiv2023

RTLLM: An Open-Source Benchmark for Design RTL Generation with Large Language Model

Inspired by the recent success of large language models (LLMs) like ChatGPT, researchers start to explore the adoption of LLMs for agile hardware design, such as generating design RTL based on natural-language instructions. However, in existing works, their target designs are all relatively simple and in a small scale, and proposed by the authors themselves, making a fair comparison among different LLM solutions challenging. In addition, many prior works only focus on the design correctness, without evaluating the design qualities of generated design RTL. In this work, we propose an open-source benchmark named RTLLM, for generating design RTL with natural language instructions. To systematically evaluate the auto-generated design RTL, we summarized three progressive goals, named syntax goal, functionality goal, and design quality goal. This benchmark can automatically provide a quantitative evaluation of any given LLM-based solution. Furthermore, we propose an easy-to-use yet surprisingly effective prompt engineering technique named self-planning, which proves to significantly boost the performance of GPT-3.5 in our proposed benchmark.

cs.LG↗