arXiv subjects

R. Casanova

Publications and source records attributed to R. Casanova.

7 recordsLinked to original sources

arXiv2026

Test-beam results from MiniCACTUS-v2: A depleted monolithic CMOS timing sensor prototype

MiniCACTUS-v2 is a monolithic sensor prototype designed in LF 150 nm CMOS process for time tagging of individual Minimum Ionizing Particles with an accuracy better than 100 ps. The sensing element is a deep n-well/p-substrate diode without internal amplification. To minimize detector capacitances, the analog front-ends and the discriminators for each pixel have been implemented outside the pixel, at the column level. After fabrication, the sensors have been thinned to 150 microns, 175 microns and 200 microns and then post-processed for backside biasing. The breakdown voltages measured on these sensors are higher than 500 V, ensuring the complete depletion of the charge collection volume. In this paper, we will focus on the time resolution measurements from a test-beam campaign conducted in July 2025 at SPS-CERN. During this period, several pixels from the 3 different sensor thicknesses have been tested at different bias voltages. The best time resolution measured is 48.88 ps on a 0.5 mm x 0.5 mm pixel from a 175 microns-thick sensor at 500 V, with nominal settings for the on-chip analog front-end and discriminator.

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arXiv2025

Enhancing Radiation Hardness and Granularity in HV-CMOS: The RD50-MPW4 Sensor

The latest HV-CMOS pixel sensor developed by the former CERN-RD50-CMOS group, known as the \mpw, demonstrates competitive radiation tolerance, spatial granularity, and timing resolution -- key requirements for future high-energy physics experiments such as the HL-LHC and FCC. Fabricated using a \SI{150}{nm} CMOS process by \emph{LFoundry}, it introduces several improvements over its predecessor, the \emph{RD50-MPW3}, including separated power domains for reduced noise, a new backside biasing scheme, and an enhanced guard ring structure, enabling operation at bias voltages up to \SI{800}{V}. Tests with non-irradiated samples achieved hit detection efficiencies exceeding \SI{99.9}{\%} and a spatial resolution around \SI{16}{\mu m}. Neutron-irradiated sensors were characterized using IV measurements and test-beam campaigns, confirming the sensor's robustness in high-radiation environments. The results highlight the ability of HV-CMOS technology to restore hit detection efficiency post-irradiation by increasing the applied bias voltage. Details of these measurements and timing performance are presented in this paper.

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arXiv2024

Characterization of the RD50-MPW4 HV-CMOS pixel sensor

The RD50-MPW4 is the latest HV-CMOS pixel sensor from the CERN-RD50-CMOS working group, designed to evaluate the HV-CMOS technology in terms of spatial resolution, radiation hardness and timing performance. Fabricated by LFoundry using a 150nm process, it features an improved architecture to mitigate crosstalk, which has been an issue with the predecessor RD50-MPW3, allowing more sensitive threshold settings and full matrix operation. Enhancements include separated power domains for peripheral and in-pixel digital readout, a new backside-biasing step, and an improved guard ring structure supporting biasing up to 500V, significantly boosting radiation hardness. Laboratory measurements and test beam results presented in this paper show significant improvements over its predecessor regarding noise behavior, spatial resolution, and efficiency.

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arXiv2021

The TaichuPix1: A Monolithic Active Pixel Sensor with fast in-pixel readout electronics for the CEPC vertex detector

The proposed Circular Electron Positron Collider (CEPC) imposes new challenges for the vertex detector in terms of high resolution, low material, fast readout and low power. The Monolithic Active Pixel Sensor (MAPS) technology has been chosen as one of the most promising candidates to satisfy these requirements. A MAPS prototype, called TaichuPix1, based on a data-driven structure, together with a column drain readout architecture, benefiting from the ALPIDE and FE-I3 approaches, has been implemented to achieve fast readout. This paper presents the overall architecture of TaichuPix1, the experimental characterization of the FE-I3-like matrix, the threshold dispersion, the noise distribution of the pixels and verifies the charge collection using a radioactive source. These results prove the functionality of the digital periphery and serializer are able to transmit the collected charge to the data interface correctly. Moreover, the individual self-tests of the serializer verify it can work up to about 3 Gbps. And it also indicates that the analog front-end features a fast-rising signal with a short time walk and that the FE-I3-like in-pixel digital logic is properly operating at the 40 MHz system clock.

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arXiv2019

Characterisation of AMS H35 HV-CMOS monolithic active pixel sensor prototypes for HEP applications

Monolithic active pixel sensors produced in High Voltage CMOS (HV-CMOS) technology are being considered for High Energy Physics applications due to the ease of production and the reduced costs. Such technology is especially appealing when large areas to be covered and material budget are concerned. This is the case of the outermost pixel layers of the future ATLAS tracking detector for the HL-LHC. For experiments at hadron colliders, radiation hardness is a key requirement which is not fulfilled by standard CMOS sensor designs that collect charge by diffusion. This issue has been addressed by depleted active pixel sensors in which electronics are embedded into a large deep implantation ensuring uniform charge collection by drift. Very first small prototypes of hybrid depleted active pixel sensors have already shown a radiation hardness compatible with the ATLAS requirements. Nevertheless, to compete with the present hybrid solutions a further reduction in costs achievable by a fully monolithic design is desirable. The H35DEMO is a large electrode full reticle demonstrator chip produced in AMS 350 nm HV-CMOS technology by the collaboration of Karlsruher Institut für Technologie (KIT), Institut de Física d'Altes Energies (IFAE), University of Liverpool and University of Geneva. It includes two large monolithic pixel matrices which can be operated standalone. One of these two matrices has been characterised at beam test before and after irradiation with protons and neutrons. Results demonstrated the feasibility of producing radiation hard large area fully monolithic pixel sensors in HV-CMOS technology. H35DEMO chips with a substrate resistivity of 200$Ω$ cm irradiated with neutrons showed a radiation hardness up to a fluence of $10^{15}$n$_{eq}$cm$^{-2}$ with a hit efficiency of about 99% and a noise occupancy lower than $10^{-6}$ hits in a LHC bunch crossing of 25ns at 150V.

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arXiv2018

Test beam measurement of ams H35 HV-CMOS capacitively coupled pixel sensor prototypes with high-resistivity substrate

In the context of the studies of the ATLAS High Luminosity LHC programme, radiation tolerant pixel detectors in CMOS technologies are investigated. To evaluate the effects of substrate resistivity on CMOS sensor performance, the H35DEMO demonstrator, containing different diode and amplifier designs, was produced in ams H35 HV-CMOS technology using four different substrate resistivities spanning from $\mathrm{80}$ to $\mathrm{1000~Ω\cdot cm}$. A glueing process using a high-precision flip-chip machine was developed in order to capacitively couple the sensors to FE-I4 Readout ASIC using a thin layer of epoxy glue with good uniformity over a large surface. The resulting assemblies were measured in beam test at the Fermilab Test Beam Facilities with 120 GeV protons and CERN SPS H8 beamline using 80 GeV pions. The in-time efficiency and tracking properties measured for the different sensor types are shown to be compatible with the ATLAS ITk requirements for its pixel sensors.

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arXiv2012

DEPFET active pixel detectors for a future linear $e^+e^-$ collider

The DEPFET collaboration develops highly granular, ultra-transparent active pixel detectors for high-performance vertex reconstruction at future collider experiments. The characterization of detector prototypes has proven that the key principle, the integration of a first amplification stage in a detector-grade sensor material, can provide a comfortable signal to noise ratio of over 40 for a sensor thickness of 50-75 $\mathrm{\mathbf{μm}}$. ASICs have been designed and produced to operate a DEPFET pixel detector with the required read-out speed. A complete detector concept is being developed, including solutions for mechanical support, cooling and services. In this paper the status of DEPFET R & D project is reviewed in the light of the requirements of the vertex detector at a future linear $\mathbf{e^+ e^-}$ collider.

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