arXiv subjects

R. Manera

Publications and source records attributed to R. Manera.

3 recordsLinked to original sources

arXiv2026

Timing performance of large prototype based on $\upmu$RWELL- PICOSEC detector technology with $10 \times 10\ \mathrm{cm}^{2}$ active area

The $\upmu$RWELL-PICOSEC detector, which combines a $\upmu$RWELL gaseous amplification structure with a Cherenkov radiator and photocathode, is a novel approach to acheive fast and precise timing in gaseous detectors. With timing precision at the level of tens of picoseconds, this technology is particularly suited for time-of-flight (TOF) applications in particle physics and potentially medical imaging. Beam tests with a 150~GeV/$c$ muon beam have been carried out on a large-area (10~$\times$~10~cm$^{2}$) prototype equipped with a cesium iodide (CsI) photocathode. Using an oscilloscope-based single-channel readout, timing measurements on two individual pads of the detector have yielded resolutions of $\approx$ 48 ps and $\approx$ 52 ps under different biasing conditions respectively.

physics.ins-det↗

arXiv2025

Challenges and strategies in verification of FastRICH ASIC for the LHCb RICH detector

The FastRICH ASIC provides high-precision, triggerless readout for the LS3 Enhancements and Upgrades II of the LHCb RICH detector. The demands of continuous data acquisition and varying hit rates across the detector impose unique challenges on the ASIC's design and verification. This work presents the verification strategy for FastRICH, focusing on functional correctness, timing performance, and operational robustness. The methodology includes simulations across occupancy scenarios, validation of timing precision, and stress testing under pile-up and high-rate conditions. Results demonstrate that FastRICH meets its performance requirements over the full range of expected occupancies. Key design and verification challenges specific to triggerless, fast-timing ASICs are discussed, along with lessons learned for future developments.

physics.ins-det↗

arXiv2025

Below 100 ps CTR using FastIC+, an ASIC including on-chip digitization for ToF-PET and beyond

This work presents the 8-channel FastIC+, a low-power consumption and highly configurable multi-channel front-end ASIC with internal digitization, for the readout of photo-sensors with picosecond time resolution and intrinsic gain. This ASIC, manufactured in 65 nm CMOS technology, can readout positive or negative polarity sensors and provides a digitized measurement of the arrival time and energy of the detected events with a power consumption of 12.5 mW per channel. On-chip digitization is executed by a Time-to-Digital Converter (TDC) based on a Phase-Locked Loop (PLL) generating 16 phases at 1.28 GHz. The internal TDC introduces a jitter contribution of 31.3 ps FWHM, with minimal impact on timing measurements. When evaluating FastIC+ to readout 3$\times$3 mm$^2$ silicon photomultipliers (SiPMs) with a pulsed laser, we achieved a single-photon time resolution (SPTR) of (98 $\pm$ 1) ps FWHM. We also performed time-of-flight positron emission tomography (ToF-PET) experiments using scintillator crystals of different sizes and materials. With LYSO:Ce,Ca crystals of 2.8$\times$2.8$\times$20 mm$^3$ we obtained a coincidence time resolution (CTR) of (130 $\pm$ 1) ps FWHM. With LGSO crystals of 2$\times$2$\times$3 mm$^3$, a CTR of (85 $\pm$ 1) ps FWHM. To the best of our knowledge, this is the first time that a CTR below 100 ps using on-chip digitization is reported.

physics.ins-det↗