arXiv subjects

Ramesh Singh Bisht

Publications and source records attributed to Ramesh Singh Bisht.

2 recordsLinked to original sources

arXiv2026

Depletion to Enhancement Mode Transition and Strongly Suppressed Hysteresis in Surface Engineered Multilayer MoS2 FETs

Two-dimensional (2D) semiconductors such as molybdenum disulfide (MoS2) have recently attracted extensive research attention due to their promising compatibility with silicon based electronics. However, several key challenges still limit their practical integration. Two of the critical issues are (1) the intrinsic depletion-mode (normally on) operation of MoS2 field-effect transistors (FETs), and (2) the large hysteresis commonly observed in the transfer characteristics of MoS2 FETs due to the inherent sulfur defects. Addressing them is essential for CMOS compatible 2D-transistor technologies. In this work, we report for the first time that surface modification of the exfoliated multilayer MoS2 FETs with PBTTT C14 (poly(2,5 bis(3 tetradecylthiophen-2-yl)thieno[3,2 b]thiophene)), a p type conjugated organic polymer, converts the device from depletion mode to enhancement mode operation while simultaneously and strongly suppressing hysteresis. Specifically, the threshold voltage (Vth) shifts from -9.6 V to +5.9 V (total shift 15.5 V), and the hysteresis window decreases from 8.8 V to 1.3 V (85% reduction). This originates from interfacial charge transfer at the MoS2/PBTTT C14 interface, enabled by favourable band alignment. To further validate this charge transfer driven mechanism, P3HT (poly(3 hexylthiophene 2,5 diyl)) with similar energy levels to PBTTT C14 was employed, and it also showed similar enhancement-mode behaviour and hysteresis suppression.

physics.app-ph↗

arXiv2023

Simulation study of various factors affecting the performance of Vertical Organic Field-Effect Transistors

Vertical field effect transistors (VOFETs) can offer short channel architecture which can further enhance the performance at low operating voltages which makes it more viable for organic electronics applications. VOFETs can be prepared with low-cost techniques which reduce the high processing costs and can also operate at high current density and relatively higher frequencies. To further improve the performance, high current density, and operating frequency the physics of charge carrier transport should be understood well with the simulation. The main problem with VOFET is the high off-current which is inevitable due to conduction from source to drain contact. There have been many efforts in reducing the off-state current by the addition of an insulating layer on top of the source electrode, which further increases the complexity and cost of processing. Simulations based on device geometry, contact barriers, and organic semiconductor parameters are carried out to study the charge carrier transport in VOFET. The simulation results show that the most important factor to enhance the performance is the device geometry or architecture, which requires a specific fill factor, a ratio between the exposed gate dielectric, and the total length with the source electrode. Optimized VOFET architecture is then simulated for variation in contact barrier and semiconductor parameters, which show some enhancement in performance but also a rise in off-state current density.

physics.app-ph↗