Constraints on Atomistic Disorder for Scalable Electron Spin Shuttling
Electron spin shuttling, the gate-controlled, coherent transport of electrons between qubit registers, increases qubit connectivity and enables efficient quantum-error-correction schemes. It is emerging as a key enabler of scalable silicon spin-qubit quantum computing. As an electron travels over micrometers, it encounters angstrom-scale disorder, causing fluctuations in its confinement potential, valley splitting, and valley phase. These lead to leakage into the valley-excited state, limiting high-fidelity shuttling speeds. Accurate predictions of shuttling fidelities thus require modeling tools that link atomistic and mesoscopic physics. We develop a multiscale simulation workflow to quantify these effects in the experimentally-realized Si/SiGe "QuBus" conveyor-belt architecture. First, we resolve the time-dependent, gate-controlled device electrostatics by solving the Poisson equation using the finite-element method. Second, we construct conveyor belt atomic structures with realistic atomistic disorder (random alloying and interface roughness); we resolve strain atomistically using the Keating valence force-field model. Third, we perform position-tracked atomistic tight-binding simulations of the shuttled electrons to obtain their time-dependent valley splittings and phases. Finally, these time traces parametrize a time-dependent Schrödinger equation, which we solve to predict valley dynamics. We find that interface roughness strongly suppresses shuttling fidelities, with a sharp anomaly near the atomic-layer scale. Overall, our predictions set practical, quantitative guidelines to realize scalable, high-fidelity shuttling in silicon spin-qubit architectures.