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Ravi Khatwal

Publications and source records attributed to Ravi Khatwal.

3 recordsLinked to original sources

Application Specific Hardware Design Simulation for High Performance Embedded System

Application specific simulation is challenging task in various real time high performance embedded devices. In this study specific application is implemented with the help of Xilinx. Xilinx provides SDK and XPS tools, XPS tools used for develop complete hardware platform and SDK provides software platform for application creation and verification. Xilinx XUP-5 board have been used and implemented various specific Applications with hardware platform. In this study the base instruction set with customized instructions, supported with specific hardware resources are analyzed.

cs.AR

Application Specific Cache Simulation Analysis for Application Specific Instruction set Processor

An Efficient Simulation of application specific instruction-set processors (ASIP) is a challenging onus in the area of VLSI design. This paper reconnoiters the possibility of use of ASIP simulators for ASIP Simulation. This proposed study allow as the simulation of the cache memory design with various ASIP simulators like Simple scalar and VEX. In this paper we have implemented the memory configuration according to desire application. These simulators performs the cache related results such as cache name, sets, cache associativity, cache block size, cache replacement policy according to specific application.

cs.AR

An Efficient Synchronous Static Memory design for Embedded System

Custom memory organization are challenging task in the area of VLSI design. This study aims to design high speed and low power consumption memory for embedded system. Synchronous SRAM has been proposed and analyzed using various simulators. Xilinx simulator simulates the Synchronous SRAM memories which can perform efficient read/write capability for embedded systems. Xinix tool also provide the access time that required selecting a word and reading it. Synchronous Static RAM which has easily read /writes capability and performs scheduled read /writes operation in efficient manner.

cs.AR