arXiv subjects

Ravi Rastogi

Publications and source records attributed to Ravi Rastogi.

10 recordsLinked to original sources

arXiv2025

Fabrication and Properties of NbN/NbNx/NbN and Nb/NbNx/Nb Josephson Junctions

Increasing integration scale of superconductor electronics (SCE) requires employing kinetic inductors and self-shunted Josephson junctions (JJs) for miniaturizing inductors and JJs. We have been developing a ten-superconductor-layer planarized fabrication process with NbN kinetic inductors and searching for suitable self-shunted JJs to potentially replace high Josephson critical current density, Jc, Nb/Al-AlOx/Nb junctions. We report on the fabrication and electrical properties of NbN/NbNx/NbN junctions produced by reactive sputtering in Ar+N2 mixture on 200-mm wafers at 200 oC and incorporated into a planarized process with two Nb ground planes and Nb wiring layer. Here NbN is a stoichiometric nitride with superconducting critical temperature Tc =15 K and NbNx is a high resistivity, nonsuperconducting nitride deposited using a higher nitrogen partial pressure than for the NbN electrodes. For comparison, we co-fabricated Nb/NbNx/Nb JJs using the same NbNx barriers deposited at 20 oC. We varied the NbNx barrier thickness from 5 nm to 20 nm, resulting in the range of Jc from about 1 mA/um^2 down to ~10 uA/um^2, and extracted coherence length of 3 nm and 4 nm in NbNx deposited, respectively at 20 oC and 200 oC. Both types of JJs are well described by resistively and capacitively shunted junction model without any excess current. We found the Jc of NbN/NbNx/NbN JJs to be somewhat lower than of Nb/NbNx/Nb JJs with the same barrier thickness, despite a much higher Tc and energy gap of NbN than of Nb electrodes. IcRn products up to ~ 0.5 mV were obtained for JJs with Jc~ 0.6 mA/um^2. Jc(T) dependences have been measured.

cond-mat.supr-con↗

arXiv2023

Development of Self-Shunted Josephson Junctions For a Ten-Superconductor-Layer Fabrication Process: Nb/NbN$_x$/Nb Junctions

To increase integration scale of superconductor electronics, we are developing a new, SFQ7ee, node of the fabrication process at MIT Lincoln Laboratory. In comparison to the existing SFQ5ee node, we increased the number of fully planarized superconducting layers to ten and utilized NbN and NbN/Nb kinetic inductors to increase the inductor number density above 100 million per cm$^2$. Increasing the Josephson junction (JJ) number density to the same level requires implementing self-shunted high-$J_c$ JJs. We investigated properties of Nb/NbN$_x$/Nb trilayer JJs as a potential replacement of high-$J_c$ Nb/Al-AlO$_x$/Nb JJs, where NbN$_x$ is a disordered, nonsuperconducting nitride deposited by reactive sputtering. Dependences of the $I_cR_n$ product and Josephson critical current density, $J_c$ on the NbN$_x$ barrier thickness and on temperature were studied in the thickness range from 5 nm to 20 nm. The fabricated JJs can be described by the microscopic theory of SNS junctions, assuming no suppression of the energy gap in Nb electrodes near the NbN$_x$ interfaces and a Cooper pair decay length in the NbN$_x$ barrier of about 2.3 nm. Current-voltage characteristics of the JJs are well described by the RCSJ model. In the studied range $J_c$ < 10 mA/$μ$$m^2$, the Nb/NbN$_x$/Nb JJs have lower specific resistance $R_nA$, lower $I_cR_n$ product, and a stronger dependence of the $I_cR_n$ on temperature than self-shunted or critically damped externally shunted Nb/Al-AlO$_x$/Nb JJs with the same critical current density; here $A$ is the JJ area, $R_n$ the JJ effective shunting resistance.

cond-mat.supr-con↗

arXiv2023

Extremely Large Area (88 mm X 88 mm) Superconducting Integrated Circuit (ELASIC)

Superconducting integrated circuit (SIC) is a promising "beyond-CMOS" device technology enables speed-of-light, nearly lossless communications to advance cryogenic (4 K or lower) computing. However, the lack of large-area superconducting IC has hindered the development of scalable practical systems. Herein, we describe a novel approach to interconnect 16 high-resolution deep UV (DUV EX4, 248 nm lithography) full reticle circuits to fabricate an extremely large (88mm X 88 mm) area superconducting integrated circuit (ELASIC). The fabrication process starts by interconnecting four high-resolution DUV EX4 (22 mm X 22 mm) full reticles using a single large-field (44 mm X 44 mm) I-line (365 nm lithography) reticle, followed by I-line reticle stitching at the boundaries of 44 mm X 44 mm fields to fabricate the complete ELASIC field (88 mm X 88 mm). The ELASIC demonstrated a 2X-12X reduction in circuit features and maintained high-stitched line superconducting critical currents. We examined quantum flux parametron (QFP) circuits to demonstrate the viability of common active components used for data buffering and transmission. Considering that no stitching requirement for high-resolution EX4 DUV reticles is employed, the present fabrication process has the potential to advance the scaling of superconducting quantum devices.

cond-mat.supr-con↗

arXiv2023

Progress toward superconductor electronics fabrication process with planarized NbN and NbN/Nb layers

To increase density of superconductor digital and neuromorphic circuits by 10x and reach integration scale of $10^8$ Josephson junctions (JJs) per chip, we developed a new fabrication process on 200-mm wafers, using self-shunted Nb/Al-AlOx/Nb JJs and kinetic inductors. The process has a layer of JJs, a layer of resistors, and 10 fully planarized superconducting layers: 8 Nb layers and 2 layers of high kinetic inductance materials, Mo$_2$N and NbN, with sheet inductance of 8 pH/sq and 3 pH/sq, respectively. NbN films were deposited by two methods: with $T_c$=15.5 K by reactive sputtering of a Nb target in Ar+N$_2$ mixture; with $T_c$ in the range from 9 K to 13 K by plasma-enhanced chemical vapor deposition (PECVD) using Tris(diethylamido)(tert-butylimido)niobium(V) metalorganic precursor. PECVD of NbN was investigated to obtain conformal deposition and filling narrow trenches and vias with high depth-to-width ratios, which was not possible to achieve using sputtering and other physical vapor deposition (PVD) methods at temperatures below $200 ^oC$ required to prevent degradation of Nb/Al-AlOx/Nb junctions. Nb layers with 200 nm thickness are used in the process layer stack as ground planes to maintain a high level of interlayer shielding and low intralayer mutual coupling, for passive transmission lines with wave impedances matching impedances of JJs, typically <=50 $Ω$, and for low-value inductors. NbN and NbN/Nb bilayer are used for cell inductors. Using NbN/Nb bilayers and individual pattering of both layers to form inductors allowed us to minimize parasitic kinetic inductance associated with interlayer vias and connections to JJs as well as to increase critical currents of the vias. Fabrication details and results of electrical characterization of NbN films, wires, and vias, and comparison with Nb properties are given.

cond-mat.supr-con↗

arXiv2023

Self- and Mutual Inductance of NbN and Bilayer NbN/Nb Inductors in Planarized Fabrication Process With Nb Ground Planes

We present measurements of the self- and mutual inductance of NbN and bilayer NbN/Nb inductors with Nb ground plane(s) fabricated in an advanced process for superconductor electronics developed at MIT Lincoln Laboratory. In this process, the signal traces of logic cell inductors are made either of a 200-nm NbN layer with $T_c$=15 K or of an in-situ deposited NbN/Nb bilayer, replacing a 200-nm Nb layer M6 in the standard SFQ5ee process with nine superconducting layers. Nb ground planes were preserved to maintain a high level of interlayer shielding and low intralayer mutual coupling. A two-step patterning of the top Nb and the bottom NbN layers of the NbN/Nb bilayer allows to create inductors in a very wide range of linear inductance values, from low values ~ 0.4 pH/$μ$m typical for Nb geometrical inductors to ~ 35 pH/$μ$m typical to thin-film kinetic inductors. Mutual inductance of NbN and Nb inductors, of NbN inductors, and of bilayer inductors is the same as between two Nb inductors with the same geometry and placement between the ground planes, i.e., mutual inductance does not depend on superconducting properties of the signal traces in the studied range of linewidths. We measured magnetic field penetration depth and kinetic inductance of NbN films with thickness t=200 nm to be $λ$ = 491+/-5 nm and 1.51 pH/sq, and 2.06 pH/sq at t=150 nm. The kinetic inductance was found to be larger than that expected for superconductors with short mean free path, indicating a reduction in the superfluid density, likely due to carrier localization effects. Kinetic inductance associated with right-angled bends of the NbN inductors is negligible at linewidths $w<λ^2/t$, indicating a very small current crowding in structures with superconducting ground plane(s). Implementation of NbN and NbN/Nb inductors can significantly increase integration scale of superconductor digital electronics.

cond-mat.supr-con↗

arXiv2019

Planarized Fabrication Process With Two Layers of SIS Josephson Junctions and Integration of SIS and SFS π-Junctions

We present our new fabrication Process for Superconductor Electronics (PSE2) that integrates two (2) layers of Josephson junctions in a fully planarized multilayer process on 200-mm wafers. The two junction layers can be, e.g., conventional Superconductor-Insulator-Superconductor (SIS) Nb/Al/AlO_x/Nb junctions with the same or different Josephson critical current densities, J_c. The process also allows integration of high-J_c Superconductor-Ferromagnet-Superconductor (SFS) or SFS'S JJs on the first junction layer with Nb/Al/AlO_x/Nb trilayer junctions on the second junction layer, or vice versa. In the present node, the SFS trilayer, Nb/Ni/Nb is placed below the standard SIS trilayer and separated by one niobium wiring layer. The main purpose of integrating the SFS and SIS junction layers is to provide compact π-phase shifters in logic cells of superconductor digital circuits and random access memories, and thereby increase the integration scale and functional density of superconductor electronics. The current node of the two-junction-layer process has six planarized niobium layers, two layers of resistors, and 350-nm minimum feature size. The target Josephson critical current densities for the SIS junctions are 100 μA/μm^2 and 200 μA/μm^2. We present the salient features of the new process, fabrication details, and characterization results on two layers of Josephson junctions integrated into one process, both for the conventional and π-junctions.

cond-mat.supr-con↗

arXiv2017

Developments Toward a 250-nm, Fully Planarized Fabrication Process With Ten Superconducting Layers And Self-Shunted Josephson Junctions

We are developing a superconductor electronics fabrication process with up to nine planarized superconducting layers, stackable stud vias, self-shunted Nb/AlOx-Al/Nb Josephson junctions, and one layer of MoNx kinetic inductors. The minimum feature size of resistors and inductors in the process is 250 nm. We present data on the mutual inductance of Nb stripline and microstrip inductors with linewidth and spacing from 250 nm to 1 μm made on the same or adjacent Nb layers, as well as the data on the linewidth and resistance uniformity.

cond-mat.supr-con↗

arXiv2012

On Stability Problems of Omega and 3-Disjoint Paths Omega Multi-stage Interconnection Networks

The research paper emphasizes that the Stable Matching problems are the same as the problems of stable configurations of Multi-stage Interconnection Networks (MIN). We have discusses the Stability Problems of Existing Regular Omega Multi-stage Interconnection Network (OMIN) and Proposed 3-Disjoint Paths Omega Multi-stage Interconnection Network (3DON) using the approaches and solutions provided by the Stable Matching Problem. Specifically, Stable Marriage Problem is used as an example of Stable Matching. On application of the concept of the Stable Marriage over the MINs states that OMIN is highly stable in comparison to 3DON.

cs.DC↗

arXiv2012

Disjoint Paths Multi-stage Interconnection Networks Stability Problem

This research paper emphasizes that the Stable Matching problems are the same as the problems of stable configurations of Multi-stage Interconnection Networks (MIN). The authors have solved the Stability Problem of Existing Regular Gamma Multi-stage Interconnection Network (GMIN), 3-Disjoint Gamma Multi-stage Interconnection Network (3DGMIN) and 3-Disjoint Path Cyclic Gamma Multi-stage Interconnection Network (3DCGMIN) using the approaches and solutions provided by the Stable Matching Problem. Specifically Stable Marriage Problem is used as an example of Stable Matching. For MINs to prove Stable two existing algorithms are used:-the first algorithm generates the MINs Preferences List in time and second algorithm produces a set of most Optimal Pairs of the Switching Elements (SEs) (derived from the MINs Preferences List) in time. Moreover, the paper also solves the problem of Ties that occurs between the Optimal Pairs. The results are promising as the comparison of the MINs based on their stability shows that the ASEN, ABN, CLN, GMIN, 3DCGMIN are highly stable in comparison to HZTN, QTN, DGMIN. However, on comparing the irregular and regular MINs in totality upon their stability the regular MINs comes out to be more stable than the irregular MINs.

cs.DC↗

arXiv2012

Case Tool: Fast Interconnections with New 3-Disjoint Paths MIN Simulation Module

Multi-stage interconnection networks (MIN) can be designed to achieve fault tolerance and collision solving by providing a set of disjoint paths. In this paper, we are discussing the new simulator added to the tool designed for developing fault tolerant MINs. The designed tool is one of its own kind and will help the user in developing 2 and 3-disjoint path networks. The java technology has been used to design the tool and have been tested on different software platform.

cs.DC↗