A Sliding Ferroelectric Resonant Tunnel Junction
Ferroelectric tunnel junctions (FTJs) leverage polarization-dependent tunneling through ultrathin barriers to enable two-terminal, non-volatile memory and logic. Although conceptually appealing, the practical implementation of conventional FTJs has been hindered by high coercive voltages, low readout currents, limited cycling endurance, and significant device-to-device variability. Here, we overcome these bottlenecks by introducing the sliding ferroelectric resonant tunnel (SFeRT) junction, integrating three cooperative mechanisms: (i) spontaneous interfacial polarization of atomically thin, depolarization-resilient barriers; (ii) superlubric sliding of shear-solitons, enabling ultra-low-friction, wear-free switching; and (iii) momentum-conserving, elastic resonant tunneling between lattice-aligned graphitic electrodes, providing sensitive readouts at both positive and negative biases. We demonstrate nanometer-scale SFeRT junctions using polar polytypes of hexagonal boron nitride (hBN) or transition metal dichalcogenides (TMDs) as barriers, achieving configurable writing voltages below $0.5$ V and tunable reading biases under $0.1$ V. These devices yield current densities exceeding $50$ nA $μ$m$^{-2}$, with a robust room-temperature ON/OFF ratio $> 7$. The crystalline and polarization integrity of sliding van der Waals (vdW) polytypes, down to the atomically thin limit, ensures exceptional device uniformity and performance that remains scalable down to sub-$0.1$ $μ$m$^{2}$ footprints. Furthermore, we provide a predictive model for SFeRT performance across diverse doping levels, temperatures, electrodes, and polytype configurations. Integrated within a Superlubric Array of Polytypes (SLAP) architecture, SFeRT junctions enable switching energies below $1$ fJ, establishing a scalable and durable foundation for low-energy ``slidetronic'' logic and memory.