arXiv subjects

Rich Rines

Publications and source records attributed to Rich Rines.

13 recordsLinked to original sources

arXiv2026

Logical Compilation for Multi-Qubit Iceberg Patches

Recent advancements in quantum computing have enabled practical use of quantum error detecting and correcting codes. However, current architectures and future proposals of quantum computer design suffer from limited qubit counts, necessitating the use of high-rate codes. Such codes, with their code parameters denoted as $[[n, k, d]]$, have more than $1$ logical qubit per code (i.e., $k > 1$). This leads to reduced error tolerance of the code, since $\lceil (d-1)/2\rceil$ errors on any of the $n$ physical qubits can affect the logical state of all $k$ logical qubits. Therefore, it becomes critical to optimally map the input qubits of a quantum circuit to these codes, in such a way that the circuit fidelity is maximized. \par However, the problem of mapping program qubits to logical qubits for high-rate codes has not been studied in prior work. A brute force search to find the optimal mapping is super exponential (scaling as $O(n!)$, where $n$ is the number of input qubits), making exhaustive search infeasible past a small number of qubits. We propose a framework that addresses this problem on two fronts: (1) for any given mapping, it performs logical-to-physical compilation that translates input gates into efficiently encoded implementations utilizing Hadamard commutation and gate merging; and (2) it quickly searches the space of possible mappings through a merge-optimizing, noise-biased packing heuristic that identifies high-performing qubit assignments without exhaustive enumeration. To the best of our knowledge, our compiler is the first work to explore mapping and compilation for high-rate codes. Across 71 benchmark circuits, we reduce circuit depth by $34\%$, gate counts by up to $31\%$ and $17\%$ for one-qubit and two-qubit gates, and improve total variation distance by $1.75\times$, with logical selection rate improvements averaging $86\%$ relative to naive compilation.

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arXiv2026

Resource Estimation via Efficient Compilation of Key Quantum Primitives

Resource estimation is a significant challenge in evaluating fault tolerant quantum computers. Existing approaches often rely on either fixed architectural assumptions or coarse analytical models that fail to capture the interaction between hardware constraints and circuit compilation. This challenge is particularly acute for neutral atom quantum computers, where architectural features such as atom movement, measurement zones, and multi-species arrays introduce a broad design space for implementing fault tolerant computation. Addressing the need for a tighter feedback loop between hardware design and practical application development, we present a compilation-driven framework for quantum resource estimation that translates arbitrary quantum circuits into logical primitive operations with known physical resource costs. This framework allows for easily configurable hardware assumptions that enable rapid comparison of different architectural design choices. We apply our approach to two early fault tolerant quantum simulation and optimization workloads, assuming the use of the surface code, revealing several architectural trends. While the production of magic states continues to be the dominant source of overhead for these benchmarks, access to movement can save time on cultivation and important transversal gates. As problem size grows, routing and qubit movement become dominant bottlenecks, highlighting the need for movement-aware compiler optimizations and frugal routing strategies. Finally, our results suggest that neutral atom architectures combining dual-species arrays with controlled qubit movement offer a promising path toward near-term advantage on fault tolerant devices.

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arXiv2026

Quantum Depth Compression via Local Dynamic Circuits

We present Quantum Depth Compression (QDC), a general compilation framework that utilizes dynamic circuits to reduce arbitrary quantum circuits to depth linear in the number of non-Clifford gates and to grid connectivity without the need for expensive SWAP-networks. The framework consists of pushing Clifford gates to the end of the circuit, resulting in a sequence of non-Clifford Pauli-phasors followed by an all Clifford sub-circuit, both of which are then reduced to constant depth via dynamic circuits. We show that applying QDC to random Pauli-phasor circuits lowers both their depth and CNOT count compared to a standard alternative compiler.

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arXiv2025

Demonstration of a Logical Architecture Uniting Motion and In-Place Entanglement

We demonstrate a logical neutral atom architecture that integrates atom motion with in-place entanglement to achieve lower overheads than entangling-zone approaches. Using a 114-qubit device, we perform three proof-of-principle logical-qubit experiments. First, we implement a pre-compiled, non-scalable variant of Shor's algorithm, observing improved logical-over-physical performance, including with loss correction and leakage detection, achieving up to a 2x reduction in TVD. Second, we construct constant-depth logical CX ladders; on current hardware these execute with serial entangling operations, yet still yield 2-4x lower error for 8 and 12 logical qubits. Third, we prepare the [[16,4,4]] code and perform single-round decoding with post-processed error correction, achieving 8x improvement on logical vs physical. These results demonstrate how combining motion with in-place entanglement offers lower overhead than entangling-zone approaches.

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arXiv2024

Fault-Tolerant Operation and Materials Science with Neutral Atom Logical Qubits

We report on the fault-tolerant operation of logical qubits on a neutral atom quantum computer, with logical performance surpassing physical performance for multiple circuits including Bell states (12x error reduction), random circuits (15x), and a prototype Anderson Impurity Model ground state solver for materials science applications (up to 6x, non-fault-tolerantly). The logical qubits are implemented via the [[4, 2, 2]] code (C4). Our work constitutes the first complete realization of the benchmarking protocol proposed by Gottesman 2016 [1] demonstrating results consistent with fault-tolerance. In light of recent advances on applying concatenated C4/C6 detection codes to achieve error correction with high code rates and thresholds, our work can be regarded as a building block towards a practical scheme for fault tolerant quantum computation. Our demonstration of a materials science application with logical qubits particularly demonstrates the immediate value of these techniques on current experiments.

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arXiv2024

Sphere Packing on a Quantum Computer for Chromatography Modeling

Column chromatography is an important process in downstream biopharmaceutical manufacturing that enables high-selectivity separation of proteins through various modalities, such as affinity, ion exchange, hydrophobic interactions, or a combination of the aforementioned modes. Current mechanistic models of column chromatography typically abstract particle-level phenomena, in particular adsorption kinetics. A mechanistic model capable of incorporating particle-level phenomena would increase the value derived from mechanistic models. To this end, we model column chromatography via sphere packing, formulating three versions, each with increasing complexity. The first, homogeneous circle packing, is recast as maximum independent set and solved by the Quantum Approximate Optimization Algorithm on a quantum computer. The second, heterogeneous circle packing, is formulated as a graphical optimization problem and solved via classical simulations, accompanied by a road map to a quantum solution. An extension to the third, heterogeneous sphere packing, is formulated mathematically in a manner suitable to a quantum solution. Finally, detailed resource scaling is conducted to estimate the quantum resources required to simulate the most realistic model, providing a pathway to quantum advantage.

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arXiv2024

Noise-Aware Circuit Compilations for a Continuously Parameterized Two-Qubit Gateset

State-of-the-art noisy-intermediate-scale quantum (NISQ) processors are currently implemented across a variety of hardware platforms, each with their own distinct gatesets. As such, circuit compilation should not only be aware of, but also deeply connect to, the native gateset and noise properties of each. Trapped-ion processors are one such platform that provides a gateset that can be continuously parameterized across both one- and two-qubit gates. Here we use the Quantum Scientific Computing Open User Testbed (QSCOUT) to study noise-aware compilations focused on continuously parameterized two-qubit $\mathcal{ZZ}$ gates (based on the M{\o}lmer-S{\o}rensen interaction) using $\textbf{Superstaq}$, a quantum software platform for hardware-aware circuit compiler optimizations. We discuss the realization of $\mathcal{ZZ}$ gates with arbitrary angle on the all-to-all connected trapped-ion system. Then we discuss a variety of different compiler optimizations that innately target these $\mathcal{ZZ}$ gates and their noise properties. These optimizations include moving from a restricted maximally entangling gateset to a continuously parameterized one, swap mirroring to further reduce total entangling angle of the operations, focusing the heaviest $\mathcal{ZZ}$ angle participation on the best performing gate pairs, and circuit approximation to remove the least impactful $\mathcal{ZZ}$ gates. We demonstrate these compilation approaches on the hardware with randomized quantum volume circuits, observing the potential to realize a larger quantum volume as a result of these optimizations. Using differing yet complementary analysis techniques, we observe the distinct improvements in system performance provided by these noise-aware compilations and study the role of stochastic and coherent error channels for each compilation choice.

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arXiv2024

Average circuit eigenvalue sampling on NISQ devices

Average circuit eigenvalue sampling (ACES) was introduced by Flammia in arXiv:2108.05803 as a protocol to characterize the Pauli error channels of individual gates across the device simultaneously. The original paper posed using ACES to characterize near-term devices as an open problem. This work advances in this direction by presenting a full implementation of ACES for real devices and deploying it to Superstaq arXiv:2309.05157, along with a device-tailored resource estimation obtained through simulations and experiments. Our simulations show that ACES is able to estimate one- and two-qubit non-uniform Pauli error channels to an average eigenvalue absolute error of under $0.003$ and total variation distance of under 0.001 between simulated and reconstructed probability distributions over Pauli errors with $10^5$ shots per circuit using 5 circuits of depth 14. The question of estimating general error channels through twirling techniques in real devices remains open, as it is dependent on a device's native gates, but simulations with the Clifford set show results in agreement with reported hardware data. Experimental results on IBM's Algiers and Osaka devices are presented, where we characterize their error channels as Pauli channels without twirling.

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arXiv2024

Q-CHOP: Quantum constrained Hamiltonian optimization

Combinatorial optimization problems that arise in science and industry typically have constraints. Yet the presence of constraints makes them challenging to tackle using both classical and quantum optimization algorithms. We propose a new quantum algorithm for constrained optimization, which we call quantum constrained Hamiltonian optimization (Q-CHOP). Our algorithm leverages the observation that for many problems, while the best solution is difficult to find, the worst feasible (constraint-satisfying) solution is known. The basic idea of Q-CHOP is to enforce a Hamiltonian constraint at all times, thereby restricting evolution to the subspace of feasible states, and slowly ``rotate'' an objective Hamiltonian to trace an adiabatic path from the worst feasible state to the best feasible state. Q-CHOP thereby assigns qualitatively distinct roles to the constraint and objective functions of a constrained optimization problem. We additionally propose a version of Q-CHOP that can start in any feasible state. Finally, we benchmark Q-CHOP against the commonly-used adiabatic algorithm of quantum annealing with an objective function that penalizes constraint violation, and find that Q-CHOP consistently performs significantly better on a wide range of problems, including textbook graph problems, knapsack problems, combinatorial auctions, and a real-world financial use case of bond exchange-traded fund basket optimization.

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arXiv2023

Superstaq: Deep Optimization of Quantum Programs

We describe Superstaq, a quantum software platform that optimizes the execution of quantum programs by tailoring to underlying hardware primitives. For benchmarks such as the Bernstein-Vazirani algorithm and the Qubit Coupled Cluster chemistry method, we find that deep optimization can improve program execution performance by at least 10x compared to prevailing state-of-the-art compilers. To highlight the versatility of our approach, we present results from several hardware platforms: superconducting qubits (AQT @ LBNL, IBM Quantum, Rigetti), trapped ions (QSCOUT), and neutral atoms (Infleqtion). Across all platforms, we demonstrate new levels of performance and new capabilities that are enabled by deeper integration between quantum programs and the device physics of hardware.

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arXiv2021

Optimized fermionic SWAP networks with equivalent circuit averaging for QAOA

The fermionic SWAP network is a qubit routing sequence that can be used to efficiently execute the Quantum Approximate Optimization Algorithm (QAOA). Even with a minimally-connected topology on an n-qubit processor, this routing sequence enables O(n^2) operations to execute in O(n) steps. In this work, we optimize the execution of fermionic SWAP networks for QAOA through two techniques. First, we take advantage of an overcomplete set of native hardware operations [including 150 ns controlled-pi/2 phase gates with up to 99.67(1)% fidelity] in order to decompose the relevant quantum gates and SWAP networks in a manner which minimizes circuit depth and maximizes gate cancellation. Second, we introduce Equivalent Circuit Averaging, which randomizes over degrees of freedom in the quantum circuit compilation to reduce the impact of systematic coherent errors. Our techniques are experimentally validated on the Advanced Quantum Testbed through the execution of QAOA circuits for finding the ground state of two- and four-node Sherrington-Kirkpatrick spin-glass models with various randomly sampled parameters. We observe a ~60% average reduction in error (total variation distance) for QAOA of depth p = 1 on four transmon qubits on a superconducting quantum processor.

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arXiv2019

Empirical determination of the simulation capacity of a near-term quantum computer

Experimentally realizable quantum computers are rapidly approaching the threshold of quantum supremacy. Quantum Hamiltonian simulation promises to be one of the first practical applications for which such a device could demonstrate an advantage over all classical systems. However, these early devices will inevitably remain both noisy and small, precluding the use of quantum error correction. We use high-performance classical tools to construct, optimize, and simulate quantum circuits subject to realistic error models in order to empirically determine the "simulation capacity" of near-term simulation experiments implemented via quantum signal processing (QSP), describing the relationship between simulation time, system size, and resolution of QSP circuits which are optimally configured to balance algorithmic precision and external noise. From simulation capacity models, we estimate maximum tolerable error rate for meaningful simulation experiments on a near-term quantum computer. By exploiting symmetry inherent to the QSP circuit, we further demonstrate that its capacity for quantum simulation can be increased by at least two orders of magnitude if errors are systematic and unitary. We find that a device with $ε^2=10^{-5}$ systematic amplitude errors could meaningfully simulate systems up to $n\approx16$ with an expected failure rate below $10\%$, whereas the largest system a device with a stochastic error rate of $p_ε=10^{-5}$ could meaningfully simulate with the same rate of failure is between $n=3$ and $n=5$ (depending on the stochastic channel). Extrapolating from empirical results, we estimate that one would typically need a stochastic error rate below $p_ε=10^{-8}$ to perform a meaningful $n=50$ simulation experiment with a failure rate below $10\%$, while the same experiment could tolerate systematic unitary errors with strength $ε^2\approx10^{-6}$.

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arXiv2018

High Performance Quantum Modular Multipliers

We present a novel set of reversible modular multipliers applicable to quantum computing, derived from three classical techniques: 1) traditional integer division, 2) Montgomery residue arithmetic, and 3) Barrett reduction. Each multiplier computes an exact result for all binary input values, while maintaining the asymptotic resource complexity of a single (non-modular) integer multiplier. We additionally conduct an empirical resource analysis of our designs in order to determine the total gate count and circuit depth of each fully constructed circuit, with inputs as large as 2048 bits. Our comparative analysis considers both circuit implementations which allow for arbitrary (controlled) rotation gates, as well as those restricted to a typical fault-tolerant gate set.

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