Rihong Zhu | Searcharxiv

arXiv2017

A high-resolution programmable Vernier delay generator based on carry chains in FPGA

This paper presents an architecture of high-resolution delay generator implemented in a single field programmable gate array (FPGA) chip by exploiting the method of utilizing dedicated carry chains. It serves as the core component in various physical instruments. The proposed delay generator contains the coarse delay step and the fine delay step to guarantee both large dynamic range and high resolution. The carry chains are organized in the Vernier delay loop style to fulfill the fine delay step with high precision and high linearity. The delay generator was implemented in the EP3SE110F1152I3 Stratix III device from Altera on a self-designed test board. Test results show the obtained resolution is 38.6 ps, and the differential nonlinearity (DNL) and integral nonlinearity (INL) is in the range of (-0.18 least significant bit (LSB),0.24 LSB)\(-0.02 LSB,0.01 LSB) under the nominal supply voltage of 1100 mV and environmental temperature of 20 degrees centigrade. The delay generator is also rather resource cost efficient which uses only 668 LUTs and 146 registers in total.

physics.ins-det↗

arXiv2017

Towards implementing multi-channels, ring-oscillator-based, Vernier time-to-digital converter in FPGAs: key design points and construction method

For TOF positron emission tomography (TOF PET) detectors, time-to-digital converters (TDCs) are essential to resolve the coincidence time of the photon pairs. Recently, an efficient TDC structure called ring-oscillator-based (RO-based) Vernier TDC using carry chains was reported by our team. The method is very promising due to its low linearity error and low resource cost. However, the implementation complexity is rather high especially when moving to multi-channels TDC designs, since this method calls for a manual intervention to the initial fitting results of the compilation software. In this paper, we elaborate the key points toward implementing high performance multi-channels TDCs of this kind while keeping the least implementation complexity. Furthermore, we propose an efficient fine time interpolator construction method called the period difference recording which only needs at most 31 adjustment trials to obtain a targeted TDC resolution. To validate the techniques proposed in this paper, we built a 32-channels TDC on a Stratix III FPGA chip and fully evaluated its performance. Code density tests show that the obtained resolution results lie in the range of (23 ps ~ 37 ps), the differential nonlinearity (DNL) results lie in the range of (-0.4 LSB ~ 0.4 LSB) and the integral nonlinearity (INL) results lie in the range of (-0.7 LSB ~ 0.7 LSB) for each of the 32 TDC channels. This paper greatly eases the designing difficulty of the carry chain RO-based TDCs and can significantly propel their development in practical use.

physics.ins-det↗