arXiv subjects

Robin Jacobs-Gedrim

Publications and source records attributed to Robin Jacobs-Gedrim.

3 recordsLinked to original sources

arXiv2026

Strong radial electric field scaling near nanoscale conductive filaments and the ReRAM resistive switching mechanism

The physics underlying reset in bipolar resistive memory has been the subject of decades of controversy and has been identified as the primary barrier to resistive memory technology development. This manuscript introduces a nanoscale effect in current carrying conductors, whereby surface charge induced radial electric fields are found to be inversely proportional to the radius of the conductive path. This nanoscale effect is then applied to explain the negative resistance switching (reset) mechanism in filamentary metal oxide resistive switching memory devices (memristors). Previous explanations for the negative resistive switching mechanism state that diffusion constitutes the radial driving mechanism for oxygen ions, and drift under electric fields is restricted to the direction parallel to current flow. This explanation conflicts with retention and microscopy data collected in a subset of devices presented in literature. We demonstrate that the electric field's dependency on the on the radius of a nanoscale conductive path can result in radial fields on the order of 10^5 to 10^6 V/cm at only -1 V bias, sufficient to govern the negative resistance switching mechanism in filamentary metal oxides. By accounting for this nanoscale size effect, long standing anomalous experimental data about the negative (reset) resistance switching mechanism in bipolar filamentary resistive memory devices is finally reconciled. Wide understanding of surface charges and associated electric fields in nanoscale conductive paths could prove important for further scaling of integrated circuits and aid in elucidating many nanoscale phenomena.

cond-mat.mes-hall↗

arXiv2025

A self-heating electrochemical cell with nine decades of programmable linear resistance

A programmable linear resistor with a compact footprint would have profound implications for microelectronics, enabling efficient in-sensor analog signal processing and in-memory computing. Non-volatile memory offers a potential solution but suffers from limitations due to the programming mechanisms that confine switching to nanoscale constrictions or field-sensitive semiconductor junctions, leading to non-linear current-voltage relationships and errors. Here, we introduce a tunable resistor that is programmed into non-volatile, high-precision resistance states spanning nine orders of magnitude, with linear current-voltage characteristics across the entire range -- significantly improving the performance and widening the application space of resistive memory. A key advance is an electrothermal gate that simultaneously spreads heat and electrochemical reactions during programming to enable large, bulk composition modulation. The volumetric modulation can host thousands of linear resistance states with 100x lower conductance errors than other memory. This enables direct processing of analog signals with high fidelity, and we demonstrate variable-gain amplification, division, and multiplication. Integration with CMOS is used to show resilience to electrical and thermal disturb in arrays and to demonstrate retention of analog levels at <1% average loss for more than 2 months across 100 devices. Simulations indicate matrix multiplication efficiency could approach >1,000 TOPS/W.

cs.ET↗

arXiv2018

Multiscale Co-Design Analysis of Energy, Latency, Area, and Accuracy of a ReRAM Analog Neural Training Accelerator

Neural networks are an increasingly attractive algorithm for natural language processing and pattern recognition. Deep networks with >50M parameters are made possible by modern GPU clusters operating at <50 pJ per op and more recently, production accelerators capable of <5pJ per operation at the board level. However, with the slowing of CMOS scaling, new paradigms will be required to achieve the next several orders of magnitude in performance per watt gains. Using an analog resistive memory (ReRAM) crossbar to perform key matrix operations in an accelerator is an attractive option. This work presents a detailed design using a state of the art 14/16 nm PDK for of an analog crossbar circuit block designed to process three key kernels required in training and inference of neural networks. A detailed circuit and device-level analysis of energy, latency, area, and accuracy are given and compared to relevant designs using standard digital ReRAM and SRAM operations. It is shown that the analog accelerator has a 270x energy and 540x latency advantage over a similar block utilizing only digital ReRAM and takes only 11 fJ per multiply and accumulate (MAC). Compared to an SRAM based accelerator, the energy is 430X better and latency is 34X better. Although training accuracy is degraded in the analog accelerator, several options to improve this are presented. The possible gains over a similar digital-only version of this accelerator block suggest that continued optimization of analog resistive memories is valuable. This detailed circuit and device analysis of a training accelerator may serve as a foundation for further architecture-level studies.

cs.AR↗