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Ron M. Roth

Publications and source records attributed to Ron M. Roth.

At least 19 recordsLinked to original sources
arXiv2026

A New Class of Geometric Analog Error Correction Codes for Crossbar Based In-Memory Computing

Analog error correction codes have been proposed for analog in-memory computing on resistive crossbars, which can accelerate vector-matrix multiplication for machine learning. Unlike traditional communication or storage channels, this setting involves a mixed noise model with small perturbations and outlier errors. A number of analog codes have been proposed for handling a single outlier, and several constructions have also been developed to address multiple outliers. However, the set of available code families remains limited, covering only a narrow range of code lengths and dimensions. In this paper, we study a recently proposed family of geometric codes capable of handling multiple outliers, and develop a geometric analysis that characterizes their m-height profiles.

cs.IT↗
arXiv2026

On the Height Profile of Analog Error-Correcting Codes

In recent work, it has been shown that maintaining reliability in analog vector--matrix multipliers can be modeled as the following coding problem. Vectors in $\mathbb{R}^k$ are encoded into codewords of a linear $[n,k,d]$ code $C$ over $\mathbb{R}$. For prescribed positive reals $\delta < \Delta$, additive errors of magnitude at most $\delta$ are tolerable and need no handling, yet outlying errors of magnitude greater than $\Delta$ are to be located or detected. The trade-off between the ratio $\Delta/\delta$ and the number of outlying errors that can be handled is determined by the height profile of $C$; as such, the height profile provides a finer description of the error handling capability of $C$, compared to the minimum distance $d$, which only determines the number of correctable errors. This work contains a further study of the notion of the height profile. Several characterizations of the height profile are presented, thereby yielding methods for computing it. The starting point is formulating this computation as an optimization problem that is solved by a set of linear programs. This, in turn, leads to a combinatorial characterization of the height profile as a maximum (or max--min) over a certain finite set of codewords of $C$. Moreover, this characterization is shown to have a simple geometric interpretation when the columns of the generator matrix of $C$ all have the same $L_2$ norm. Through examples of several code families, it is demonstrated how the results herein can be used to compute the height profile explicitly.

cs.IT↗
arXiv2025

NL-DPE: An Analog In-memory Non-Linear Dot Product Engine for Efficient CNN and LLM Inference

Resistive Random Access Memory (RRAM) based in-memory computing (IMC) accelerators offer significant performance and energy advantages for deep neural networks (DNNs), but face three major limitations: (1) they support only \textit{static} dot-product operations and cannot accelerate arbitrary non-linear functions or data-dependent multiplications essential to modern LLMs; (2) they demand large, power-hungry analog-to-digital converter (ADC) circuits; and (3) mapping model weights to device conductance introduces errors from cell nonidealities. These challenges hinder scalable and accurate IMC acceleration as models grow. We propose NL-DPE, a Non-Linear Dot Product Engine that overcomes these barriers. NL-DPE augments crosspoint arrays with RRAM-based Analog Content Addressable Memory (ACAM) to execute arbitrary non-linear functions and data-dependent matrix multiplications in the analog domain by transforming them into decision trees, fully eliminating ADCs. To address device noise, NL-DPE uses software-based Noise Aware Fine-tuning (NAF), requiring no in-device calibration. Experiments show that NL-DPE delivers 28X energy efficiency and 249X speedup over a GPU baseline, and 22X energy efficiency and 245X speedup over existing IMC accelerators, while maintaining high accuracy.

cs.AR↗
arXiv2025

New Bounds and Constructions for Variable Packet-Error Coding

In this paper, we consider the problem of variable packet-error coding, which emerges in network communication scenarios where a source transmits information to a destination through multiple disjoint paths. The objective is to design codes with dynamic error-correcting capabilities that adapt to varying numbers of errors. Specifically, we first provide several bounds on the rate--distortion trade-off for general variable packet-error coding schemes. Then, we present two explicit constructions of variable packet-error coding schemes. The first construction uses higher-order MDS codes and provides a coding scheme that achieves a better rate--distortion trade-off compared to known results for general parameter regimes. The second construction is based on a variant of the repetition code and yields a coding scheme with an optimal rate--distortion trade-off, with respect to our bound, for certain parameter regimes.

cs.IT↗
arXiv2024

On Nearly Perfect Covering Codes

Nearly perfect packing codes are those codes that meet the Johnson upper bound on the size of error-correcting codes. This bound is an improvement to the sphere-packing bound. A related bound for covering codes is known as the van Wee bound. Codes that meet this bound will be called nearly perfect covering codes. In this paper, such codes with covering radius one will be considered. It will be proved that these codes can be partitioned into three families depending on the smallest distance between neighboring codewords. Some of the codes contained in these families will be completely characterized. Other properties of these codes will be considered too. Construction for codes for each such family will be presented, the weight distribution and the distance distribution of codes from these families are characterized. Finally, extended nearly perfect covering code will be considered and unexpected equivalence classes of codes of the three types will be defined based on the extended codes.

cs.IT↗
arXiv2024

Multiple-Error-Correcting Codes for Analog Computing on Resistive Crossbars

Error-correcting codes over the real field are studied which can locate outlying computational errors when performing approximate computing of real vector--matrix multiplication on resistive crossbars. Prior work has concentrated on locating a single outlying error and, in this work, several classes of codes are presented which can handle multiple errors. It is first shown that one of the known constructions, which is based on spherical codes, can in fact handle multiple outlying errors. A second family of codes is then presented with $\zeroone$~parity-check matrices which are sparse and disjunct; such matrices have been used in other applications as well, especially in combinatorial group testing. In addition, a certain class of the codes that are obtained through this construction is shown to be efficiently decodable. As part of the study of sparse disjunct matrices, this work also contains improved lower and upper bounds on the maximum Hamming weight of the rows in such matrices.

cs.IT↗
arXiv2023

RACE-IT: A Reconfigurable Analog Computing Engine for In-Memory Transformer Acceleration

Transformer models represent the cutting edge of Deep Neural Networks (DNNs) and excel in a wide range of machine learning tasks. However, processing these models demands significant computational resources and results in a substantial memory footprint. While In-memory Computing (IMC)offers promise for accelerating Vector-Matrix Multiplications(VMMs) with high computational parallelism and minimal data movement, employing it for other crucial DNN operators remains a formidable task. This challenge is exacerbated by the extensive use of complex activation functions, Softmax, and data-dependent matrix multiplications (DMMuls) within Transformer models. To address this challenge, we introduce a Reconfigurable Analog Computing Engine (RACE) by enhancing Analog Content Addressable Memories (ACAMs) to support broader operations. Based on the RACE, we propose the RACE-IT accelerator (meaning RACE for In-memory Transformers) to enable efficient analog-domain execution of all core operations of Transformer models. Given the flexibility of our proposed RACE in supporting arbitrary computations, RACE-IT is well-suited for adapting to emerging and non-traditional DNN architectures without requiring hardware modifications. We compare RACE-IT with various accelerators. Results show that RACE-IT increases performance by 453x and 15x, and reduces energy by 354x and 122x over the state-of-the-art GPUs and existing Transformer-specific IMC accelerators, respectively.

cs.AR↗
arXiv2023

On the Implementation of Boolean Functions on Content-Addressable Memories

Let $[q\rangle$ denote the integer set $\{0,1,\ldots,...,q-1\}$ and let $\mathbb{B}=\{0,1\}$. The problem of implementing functions $[q\rangle\rightarrow\mathbb{B}$ on content-addressable memories (CAMs) is considered. CAMs can be classified by the input alphabet and the state alphabet of their cells; for example, in binary CAMs, those alphabets are both $\mathbb{B}$, while in a ternary CAM (TCAM), both alphabets are endowed with a "don't care" symbol. This work is motivated by recent proposals for using CAMs for fast inference on decision trees. In such learning models, the tree nodes carry out integer comparisons, such as testing equality ($x=t$?) or inequality ($x\le t$?), where $x \in [q\rangle$ is an input to the node and $t \in [q\rangle$ is a node parameter. A CAM implementation of such comparisons includes mapping (i.e., encoding) $t$ into internal states of some number $n$ of cells and mapping $x$ into inputs to these cells, with the goal of minimizing $n$. Such mappings are presented for various comparison families, as well as for the set of all functions $[q\rangle\rightarrow\mathbb{B}$, under several scenarios of input and state alphabets of the CAM cells. All those mappings are shown to be optimal in that they attain the smallest possible $n$ for any given $q$.

cs.DM↗
arXiv2023

X-TIME: An in-memory engine for accelerating machine learning on tabular data with CAMs

Structured, or tabular, data is the most common format in data science. While deep learning models have proven formidable in learning from unstructured data such as images or speech, they are less accurate than simpler approaches when learning from tabular data. In contrast, modern tree-based Machine Learning (ML) models shine in extracting relevant information from structured data. An essential requirement in data science is to reduce model inference latency in cases where, for example, models are used in a closed loop with simulation to accelerate scientific discovery. However, the hardware acceleration community has mostly focused on deep neural networks and largely ignored other forms of machine learning. Previous work has described the use of an analog content addressable memory (CAM) component for efficiently mapping random forests. In this work, we develop an analog-digital architecture that implements a novel increased precision analog CAM and a programmable chip for inference of state-of-the-art tree-based ML models, such as XGBoost, CatBoost, and others. Thanks to hardware-aware training, X-TIME reaches state-of-the-art accuracy and 119x higher throughput at 9740x lower latency with >150x improved energy efficiency compared with a state-of-the-art GPU for models with up to 4096 trees and depth of 8, with a 19W peak power consumption.

cs.LG↗
arXiv2021

Higher-Order MDS Codes

An improved Singleton-type upper bound is presented for the list decoding radius of linear codes, in terms of the code parameters [n,k,d] and the list size L. L-MDS codes are then defined as codes that attain this bound (under a slightly stronger notion of list decodability), with 1-MDS codes corresponding to ordinary linear MDS codes. Several properties of such codes are presented; in particular, it is shown that the 2-MDS property is preserved under duality. Finally, explicit constructions for 2-MDS codes are presented through generalized Reed-Solomon (GRS) codes.

cs.IT↗
arXiv2021

Variable-Length Constrained Coding and Kraft Conditions: The Parity-Preserving Case

Previous work by the authors on parity-preserving fixed-length constrained encoders is extended to the variable-length case. Parity-preserving variable-length encoders are formally defined, and, to this end, Kraft conditions are developed for the parity-preserving variable-length setting. Then, a necessary and sufficient condition is presented for the existence of deterministic parity-preserving variable-length encoders for a given constraint. Examples are provided that show that there are coding ratios where parity-preserving variable-length encoders exist, while fixed-length encoders do not.

cs.IT↗
arXiv2021

On the Number of Factorizations of Polynomials over Finite Fields

Motivated by coding applications,two enumeration problems are considered: the number of distinct divisors of a degree-m polynomial over F = GF(q), and the number of ways a polynomial can be written as a product of two polynomials of degree at most n over F. For the two problems, bounds are obtained on the maximum number of factorizations, and a characterization is presented for polynomials attaining that maximum. Finally, expressions are presented for the average and the variance of the number of factorizations, for any given m (respectively, n).

cs.DM↗
arXiv2020

Asymptotic Bounds on the Rate of Locally Repairable Codes

New asymptotic upper bounds are presented on the rate of sequences of locally repairable codes (LRCs) with a prescribed relative minimum distance and locality over a finite field $F$. The bounds apply to LRCs in which the recovery functions are linear; in particular, the bounds apply to linear LRCs over $F$. The new bounds are shown to improve on previously published results, especially when the repair groups are disjoint, namely, they form a partition of the set of coordinates.

cs.IT↗
arXiv2020

On Bi-Modal Constrained Coding

Bi-modal (respectively, multi-modal) constrained coding refers to an encoding model whereby a user input block can be mapped to two (respectively, multiple) codewords. In current storage applications, such as optical disks, multi-modal coding allows to achieve DC control, in addition to satisfying the runlength limited (RLL) constraint specified by the recording channel. In this work, a study is initiated on bi-modal fixed-length constrained encoders. Necessary and sufficient conditions are presented for the existence of such encoders for a given constraint. It is also shown that under somewhat stronger conditions, one can guarantee a bi-modal encoder with finite decoding delay.

cs.IT↗
arXiv2017

Fault-Tolerant Dot-Product Engines

Coding schemes are presented that provide the ability to correct and detect computational errors while using dot-product engines for integer vector--matrix multiplication. Both the $L_1$-metric and the Hamming metric are considered.

cs.IT↗
arXiv2017

Construction of Sidon spaces with applications to coding

A subspace of a finite extension field is called a Sidon space if the product of any two of its elements is unique up to a scalar multiplier from the base field. Sidon spaces were recently introduced by Bachoc et al. as a means to characterize multiplicative properties of subspaces, and yet no explicit constructions were given. In this paper, several constructions of Sidon spaces are provided. In particular, in some of the constructions the relation between $k$, the dimension of the Sidon space, and $n$, the dimension of the ambient extension field, is optimal. These constructions are shown to provide cyclic subspace codes, which are useful tools in network coding schemes. To the best of the authors' knowledge, this constitutes the first set of constructions of non-trivial cyclic subspace codes in which the relation between $k$ and $n$ is polynomial, and in particular, linear. As a result, a conjecture by Trautmann et al. regarding the existence of non-trivial cyclic subspace codes is resolved for most parameters, and multi-orbit cyclic subspace codes are attained, whose cardinality is within a constant factor (close to $1/2$) from the sphere-packing bound for subspace codes.

cs.IT↗
arXiv2014

Coding for Combined Block-Symbol Error Correction

We design low-complexity error correction coding schemes for channels that introduce different types of errors and erasures: on the one hand, the proposed schemes can successfully deal with symbol errors and erasures, and, on the other hand, they can also successfully handle phased burst errors and erasures.

cs.IT↗