Knowledge Distillation of a Normalising Flow for Real-Time Anomaly Detection at LHC Level-1 Trigger
We present a new strategy for unsupervised anomaly detection at the hardware-based first stage of event processing (Level-1 trigger) of the Large Hadron Collider (LHC). A normalising flow trained exclusively on Standard Model (SM) events provides a teacher anomaly score based on its exact negative log-likelihood, which is distilled into a compact neural network suitable for field-programmable gate array (FPGA) deployment. The teacher reaches state-of-the-art performance on a benchmark dataset, using a rigorous p-value-based definition of the anomaly score. A simple two-hidden-layer student reproduces the teacher performance across four beyond-the-SM benchmarks to within 0.1 percentage points in area under the receiver operating characteristic curve (AUC), while achieving a compression factor of approximately 325 times. Quantisation-aware training with PQuantML reduces the model to 8-bit precision with AUC changes below 0.06 percentage points. Compilation to Verilog firmware with Alkaid yields FPGA designs that require neither digital signal processors nor block random-access memory and achieve latencies of 27-52 ns. This modular pipeline decouples the expressiveness of the anomaly-detection model from real-time hardware constraints, enabling complex architectures to be used for model-agnostic searches for new physics at the full LHC collision rate of 40 MHz.