arXiv subjects

Roshan Padhan

Publications and source records attributed to Roshan Padhan.

3 recordsLinked to original sources

arXiv2026

CVD grown bilayer MoS2 based artificial optoelectronic synapses for arithmetic computing and image recognition applications

Demand for lower computing power has rapidly increased. In this context, brain-inspired neuromorphic computing, which integrate data storage and processing, has attracted significant attention. Here, our study reveals that field effect transistors fabricated on chemical vapor deposited bilayer (2L) MoS2 films can mimic the functions of biological synapse. These devices demonstrate high level of pair pulse facilitation (PPF), short term to long term memory (STM-to-LTM) transition as well as learning-forgetting-relearning properties. Effect of light intensity, pulse number, pulse width and photon energy on the STM-to-LTM transition is studied. It has been found that the rate of depression of the memory state can be controlled using the gate bias. Electrical and optical energy consumptions per synaptic event are estimated to be as low as 280 fJ and 20 nJ, respectively. Furthermore, photocurrent in these devices is observed to increase linearly with the number of the excitation pulses. This property has been exploited to demonstrate different arithmetic operations by the device. Moreover, these devices show great potential for image recognition. Artificial neural network simulation has returned an image recognition accuracy of ~85%. All these findings show a great prospect of 2L-MoS2 for developing low power, transparent and flexible neuromorphic devices.

cond-mat.mtrl-sci↗

arXiv2023

A facile direct device transfer of monolayer MoS2 towards improvement in transistor performances

Transfer techniques based on two dimensional (2D) materials and devices offer immense potential towards their industrial integration with the existing silicon based electronics. To achieve high quality devices, there is an urgent requirement for the etching-free, and clean transfer that retain original semiconducting properties of layered channel materials. In parallel, transfer of metal electrode arrays on the 2D semiconductors also attract attention towards large-scale integration for commercial applications. Here, we demonstrate a facile PMMA-assisted etching-free one-step approach to transfer both 2D channels and metal electrodes without damaging the contact region. The direct device transfer (DDT) technique enables residue-free monolayer MoS2 as channel material towards achieving doping-free intrinsic transistors with enhanced performances. The crystalline quality, strain relaxation, and interfacial coupling effects are studied using Raman and photoluminescence spectra with spatial mapping. Post device transfer, a reduced pinning effect is observed by the effective modulation of gate tunable drain currents in MoS2 transistors at room temperature. Furthermore, the extracted Schottky barrier heights, temperature dependence of threshold voltage shifts, hysteresis evolution, and mobility enhancements validates the improved transistor performances in transferred devices. The proposed DDT method can be utilized to directly transfer array of devices of 2D materials and heterostructures skipping various cumbersome steps in between and hence could offer high performance reliable electronic applications.

cond-mat.mes-hall↗

arXiv2023

Thermally-driven Multilevel Non-volatile Memory with Monolayer MoS2 for Neuro-inspired Artificial Learning

The demands of modern electronic components require advanced computing platforms for efficient information processing to realize in-memory operations with a high density of data storage capabilities towards developing alternatives to von Neumann architectures. Herein, we demonstrate the multifunctionality of monolayer MoS2 mem-transistors which can be used as a high-geared intrinsic transistor at room temperature; however, at a high temperature (>350 K), they exhibit synaptic multi-level memory operations. The temperature-dependent memory mechanism is governed by interfacial physics, which solely depends on the gate field modulated ion dynamics and charge transfer at the MoS2/dielectric interface. We have proposed a non-volatile memory application using a single FET device where thermal energy can be ventured to aid the memory functions with multi-level (3-bit) storage capabilities. Furthermore, our devices exhibit linear and symmetry in conductance weight updates when subjected to electrical potentiation and depression. This feature has enabled us to attain a high classification accuracy while training and testing the Modified National Institute of Standards and Technology datasets through artificial neural network simulation. This work paves the way for new avenues in 2D semiconductors toward reliable data processing and storage with high-packing density arrays for brain-inspired artificial learning.

cond-mat.mes-hall↗