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Roza Kotlyar

Publications and source records attributed to Roza Kotlyar.

4 recordsLinked to original sources

Solid-state transcapacitor, a new gain element for logic, memory and interconnects

Today's transistors dictate the voltage and charge scales for both logic and memory. While AI systems are recognized to be limited by memory energy, the dominant share of the energy is expended in the intrachip interconnects whose voltage and charge scales are set by transistors. The energy scaling challenges of transistors can be attributed to simultaneously meeting high current density, high current/impedance modulation, and the inability to lower voltages. Hence, a new logic element that lowers the voltage and charge needs is a priority, not only for lowering logic power but also memory access power. Here, we propose a novel 3-terminal logic element for low energy computing, a solid-state transcapacitor (TCAP). A TCAP is a solid state displacement current modulator realized by a gate which controls the charge-voltage relationship of the channel. Unlike transistors, TCAPs eliminate the dissipative transport current, are not bound by the Boltzmann current modulation limit, and operate with displacement currents limited only by the polarization response and contact resistance. Hence, TCAP circuits may simultaneously overcome the voltage, current density, and current modulation limits of CMOS. We describe a solid state TCAP using a piezoelectric transcapacitor in which a gate-controlled stressor modulates the capacitance of a polar channel via electromechanical coupling. This device achieves inversion and gain, essential for logic, and is functionally equivalent to a 1T-1C memory cell, enabling dense memory. Using voltage scaling, capacitive energy recovery, and high polarization densities of polar materials, the logic based on TCAP offers a pathway to 100 fold lower energy consumption with a delay comparable to ultimately scaled CMOS devices. This approach provides a new potential pathway for low-energy computing beyond the limits of transistors using electro-mechanics and multiferroics.

cond-mat.mes-hall

Fast quantum gates for exchange-only qubits using simultaneous exchange pulses

The benefit of exchange-only qubits compared to other spin qubit types is the universal control using only voltage controlled exchange interactions between neighboring spins. As a compromise, qubit operations have to be constructed from non-orthogonal rotation axes of the Bloch sphere and result in rather long pulsing sequences. This paper aims to develop a faster implementation of single-qubit gates using simultaneous exchange pulses and manifests their potential for the construction of two-qubit gates. We introduce pulse sequences in which single-qubit gates could be executed faster and show that subsequences on three spins in two-qubit gates could be implemented in fewer steps. Our findings can particularly speed up gate sequences for realistic idle times between sequential pulses and we show that this advantage increases with more interconnectivity of the quantum dots. We further demonstrate how a phase operation can introduce a relative phase between the computational and some of the leakage states, which can be advantageous for the construction of two-qubit gates. In addition to our theoretical analysis, we experimentally demonstrate and characterize a simultaneous exchange implementation of $X$ rotations in a SiGe quantum dot device and compare to the state of the art with sequential exchange pulses.

quant-ph

Probing single electrons across 300 mm spin qubit wafers

Building a fault-tolerant quantum computer will require vast numbers of physical qubits. For qubit technologies based on solid state electronic devices, integrating millions of qubits in a single processor will require device fabrication to reach a scale comparable to that of the modern CMOS industry. Equally importantly, the scale of cryogenic device testing must keep pace to enable efficient device screening and to improve statistical metrics like qubit yield and voltage variation. Spin qubits based on electrons in Si have shown impressive control fidelities but have historically been challenged by yield and process variation. Here we present a testing process using a cryogenic 300 mm wafer prober to collect high-volume data on the performance of hundreds of industry-manufactured spin qubit devices at 1.6 K. This testing method provides fast feedback to enable optimization of the CMOS-compatible fabrication process, leading to high yield and low process variation. Using this system, we automate measurements of the operating point of spin qubits and probe the transitions of single electrons across full wafers. We analyze the random variation in single-electron operating voltages and find that the optimized fabrication process leads to low levels of disorder at the 300 mm scale. Together these results demonstrate the advances that can be achieved through the application of CMOS industry techniques to the fabrication and measurement of spin qubit devices.

quant-ph

A thermodynamic theory of filamentary resistive switching

We present a phenomenological theory of filamentary resistive random access memory (RRAM) describing the commonly observed features of their current-voltage characteristics. Our approach follows the approach of thermodynamic theory developed earlier for chalcogenide memory and threshold switches and largely independent of their microscopic details. It explains, without adjustable parameters, such features as the domains of filament formation and switching, voltage independent current in SET and current independent voltage in RESET regimes, the relation between the set and reset voltages, filament resistance independent of its length, etc. Furthermore, it expresses the observed features through the material and circuitry parameters thus paving a way to device improvements.

cond-mat.mes-hall