arXiv subjects

Rozita Teymourzadeh

Publications and source records attributed to Rozita Teymourzadeh.

At least 19 recordsLinked to original sources

arXiv2025

A Scalable and Interoperable Platform for Transforming Building Information with Brick Ontology

In the digital twin and building information era, many building automation companies searched for scalable methods to extract and analyze different building data, including Internet of Things (IoT) sensors, actuators, layout sections, zones, etc. The necessity for engineers to continuously manage the entire process for each new building creates scalability challenges. Furthermore, because construction information is sensitive, transferring data on vendor platforms via the cloud creates problems. This paper introduces a platform designed to address some of the common challenges in building automation. This is a smart platform designed for the transformation of building information into Brick ontology (Brick 2020) and graph formats. This technology makes it easy to retrieve historical data and converts the building point list into a Brick schema model for use in digital twin applications. The overarching goal of the proposed platform development is semi-automate the process while offering adaptability to various building configurations. This platform uses Brick schema and graph data structure techniques to minimize complexity, offering a semi-automated approach through its use of a tree-based graph structure. Moreover, the integration of Brick ontology creates a common language for interoperability and improves building information management. The seamless and offline integration of historical data within the developed platform minimizes data security risks when handling building information.

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arXiv2018

Design an Advance computer-aided tool for Image Authentication and Classification

Over the years, advancements in the fields of digital image processing and artificial intelligence have been applied in solving many real-life problems. This could be seen in facial image recognition for security systems, identity registrations. Hence a bottleneck of identity registration is image processing. These are carried out in form of image preprocessing, image region extraction by cropping, feature extraction using Principal Component Analysis (PCA) and image compression using Discrete Cosine Transform (DCT). Other processing includes filtering and histogram equalization using contrast stretching is performed while enhancing the image as part of the analytical tool. Hence, this research work presents a universal integration image forgery detection analysis tool with image facial recognition using Back Propagation Neural Network (BPNN) processor. The proposed designed tool is a multi-function smart tool with the novel architecture of programmable error goal and light intensity. Furthermore, its advance dual database increases the efficiency of a high-performance application. With the fact that, the facial image recognition will always, give a matching output or closest possible output image for every input image irrespective of the authenticity, the universal smart GUI tool is proposed and designed to perform image forgery detection with the high accuracy of 2% error rate. Meanwhile, a novel structure that provides efficient automatic image forgery detection for all input test images for the BPNN recognition is presented. Hence, an input image will be authenticated before being fed into the recognition tool.

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arXiv2018

VLSI Design Of Advanced Digital Filters

The Cascaded Integrator Comb filters (CIC) find many applications in recent electronic devices such as frequency selection functions in a digital radio or modem and any filter structure that is required to efficiently process large sample rate factor. These filters are normally located after the sigma-delta modulator and have a regular structure. These types of filters do not require multipliers and the coefficient storage unlike in the normal digital FIR and IIR filters because of all filter coefficients are unity. Hence, it can be efficiently implemented to operate at high speed. Hence, this book describes the Very Large Scale Integration (VLSI) implementation of the CIC filters that are suitable for high-performance audio applications.

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arXiv2018

Advanced Frequency Identification Power Metering System for Energy Usage

Energy meter measures the amount of power consumed by electrical loads in residential, industrial and commercial applications. In this project, the focus goes to the implementation of a smart power measurement system to allocate identification for individuals and determine the clients energy usage. The incorporation of two PIC 16F877A microcontrollers and radio-frequency identification (RFID) reader in this research work make the system operation smooth and reliable. This paper presents the development of an intelligent prepaid power metering system enabling power utilities to collect electricity bills from consumers prior to the usage of power. Homeowners are able to monitor reliable power consumption data for efficient power management. To conclude, a graphical user interface (GUI) has been designed to be applied for data transmission between the personal computer and RFID a smart card which allows the credit to be transferred to the smart card.

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arXiv2018

Static Quantized Radix-2 FFT/IFFT Processor for Constraints Analysis

This research work focuses on the design of a high-resolution fast Fourier transform (FFT) /inverse fast Fourier transform (IFFT) processors for constraints analysis purpose. Amongst the major setbacks associated with such high resolution, FFT processors are the high power consumption resulting from the structural complexity and computational inefficiency of floating-point calculations. As such, a parallel pipelined architecture was proposed to statically scale the resolution of the processor to suite adequate trade-off constraints. The quantization was applied to provide an approximation to address the finite word-length constraints of digital signal processing (DSP). An optimum operating mode was proposed, based on the signal-to-quantization-noise ratio (SQNR) as well as the statistical theory of quantization, to minimize the tradeoff issues associated with selecting the most application-efficient floating-point processing capability in contrast to their resolution quality.

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arXiv2018

Universal Computer aided design for electrical machines

Electrical machines are devices that change either mechanical or electrical energy to the other and also can alternate the voltage levels of an alternating current. The need for electrical machines cannot be overemphasized since they are used in various applications in the world today. Its design is to meet the specifications as stated by the user and this design has to be an economical one. The design, therefore, revolves around designing the machine to meet the stipulated performance required, the cost available and the lasting life of the machine. This work aims to eliminate the tediousness involved in the manual hand calculations of designing the machines by making use of a graphical user interface and using iterations in situations where the data would have been assumed.

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arXiv2018

Smart Novel Computer-based Analytical Tool for Image Forgery Authentication

This paper presents an integration of image forgery detection with image facial recognition using black propagation neural network (BPNN). We observed that facial image recognition by itself will always give a matching output or closest possible output image for every input image irrespective of the authenticity or otherwise not of the testing input image. Based on this, we are proposing the combination of the blind but powerful automation image forgery detection for entire input images for the BPNN recognition program. Hence, an input image must first be authenticated before being fed into the recognition program. Thus, an image security identification and authentication requirement, any image that fails the authentication/verification stage are not to be used as an input/test image. In addition, the universal smart GUI tool is proposed and designed to perform image forgery detection with the high accuracy of 2% error rate.

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arXiv2018

High linear low noise amplifier based on self-biasing multiple gated transistors

Noise level frequently set the basic limit on the smallest signal. New noise reduction technology and amplifiers voltage-noise density, yet still offer high speed, high accuracy, and low power solution. Low noise amplifiers always play a significant role in RF technology. Hence in this paper, high linear low noise amplifier (LNA) using cascade self-biased multiple gated transistors (MGTR) is presented. The proposed system is covering 0.9 to 2.4 GHz applications. To verify the functionality of the proposed LNA as a bottleneck of RF technology, a cascade LNA without MGTR is implemented and synthesized. The comparison has been done with the single-gate LNA. From the synthesized result, proposed LNA obtained 10 dBm third-order input intercept point (IIP3) in compare with single-gate LNA at 9dB gain. The proposed LNA is implemented in 90 nm CMOS technology and reported 13 dBm IIP3, 1.9 dB NF and 9 dB gain while consuming 7.9 mW from 2 V supply.

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arXiv2018

Mathematical Toolbox and its application in the Development of Laboratory Scale Vertical Axis Wind Turbine

A wind turbine works with the principle of extracting energy from the wind to generate electricity. The power generated is directly proportional to the wind speed available. There are two major types of wind turbine design namely the horizontal and vertical axis wind turbine depending on the orientation of the turbine rotor and its generator. This paper deals with the design of vertical turbine due to its advantage of operating at a low wind speed over that of the horizontal turbine. The analysis of change in the parameters of a vertical axis wind turbine is investigated to get the optimized way in which the rotor of the turbine is to be designed. This is done through modeling and simulation of the turbine using various parameters in the MATLAB/SIMULINK environment. A graphical user interface is created for a generic model of vertical axis wind turbine that is used to determine its parameters.

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arXiv2018

RFID-BASED Prepaid Power Meter

An Electric power meter is an important component in electric energy service. In the past, many consumers have complained about reading inaccurate of the electric meter. This research presents the development of an electrical power meter equipped with RFID reader. The RFID reader reads a valid RFID card and activates the power meter so that it can supply electricity. When the credit is about low or before the electricity is auto cut off, an SMS message will be sent to the users handphone to alert.

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arXiv2018

Novel Architecture of Pipeline Radix 2 power of 2 SDF FFT Based on Digit-Slicing Technique

The prevalent need for very high-speed digital signals processing in wireless communications has driven the communications system to high-performance levels. The objective of this paper is to propose a novel structure for efficient implementation for the Fast Fourier Transform (FFT) processor to meet the requirement for high-speed wireless communication system standards. Based on the algorithm, architecture analysis, the design of pipeline Radix 2power of 2 SDF FFT processor based on digit-slicing Multiplier-Less is proposed. Furthermore, this paper proposed an optimal constant multiplication arithmetic design to multiply a fixed point input selectively by one of the several present twiddle factor constants. The proposed architecture was simulated using MATLAB software and the Field Programmable Gate Array (FPGA) Virtex 4 was targeted to synthesis the proposed architecture. The design was tested in real hardware of TLA5201 logic analyzer and the ISE synthesis report results the high speed of 669.277 MHz with the total equivalent gate count of 14,854. Meanwhile, It can be found as significant improvement over Radix 22 DIF SDF FFT processor and can be concluded that the proposed pipeline Radix 22 DIF SDF FFT processor based on digit-slicing multiplier-less is an enable in solving problems that affect the most high-speed wireless communication systems capability in FFT and possesses huge potentials for future related works and research areas.

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arXiv2018

Planar Dipole Antenna Design At 1800MHz Band Using Different Feeding Methods For GSM Application

This research work focuses on the design and simulation of a planar dipole antenna for 1800MHZ Band for Global System Mobile GSM application using Computer Software Technology CST studio software. The antenna is structured on a fire resistance FR4 substrate with a relative constant of 4.3 S/m. Two types of feeding configuration are designed to feed the antenna in order to match 50 ohm transmission lines which are via-hole integrated balun and quarter wavelength open stub. The via-hole is capable to provide maximum return loss of 25dB, bandwidth of 18.4 percent and the voltage standing wave ratio (VSWR) of 1.116 V at optimum dimension of length 59mm and width 4mm, the bandwidth is improved 25 percent to 30 percent by extending the width of the antenna 8 mm to 10 mm followed by deterioration of return loss value to 15dB. While the open stub at length of 67 mm, the width of 6 mm and height 1.6mm will provide max return loss of 47.88dB and bandwidth of 17 percent with VSWR 1.008 less than 2. The way that the antenna substrate has influenced the performance of the antenna. The lower relative constant will result in the higher return lows, narrower bandwidth and better radiation pattern in trade-off the resonant length Via-hole and then the quarter wave open stub are most convenient for practical implementation.

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arXiv2018

Characteristic Analysis of 1024-Point Quantized Radix-2 FFT/IFFT Processor

The precise analysis and accurate measurement of harmonic provides a reliable scientific industrial application. However, the high-performance DSP processor is the important method of electrical harmonic analysis. Hence, in this research work, the effort was taken to design a novel high-resolution single 1024-point fast Fourier transform (FFT) and inverse fast Fourier transform (IFFT) processors for improvement of the harmonic measurement techniques. Meanwhile, the project is started with design and simulation to demonstrate the benefit that is achieved by the proposed 1024-point FFT/IFFT processor. The pipelined structure is incorporated in order to enhance the system efficiency. As such, a pipelined architecture was proposed to statically scale the resolution of the processor to suite adequate trade-off constraints. The proposed FFT makes use of programmable fixed-point/floating-point to realize higher precision FFT.

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arXiv2018

Smart Analytical Signature Verification For DSP Applications

Signature verification is an authentication technique that considers handwritten signature as a biometric. From a biometric perspective this project made use of automatic means through an integration of intelligent algorithms to perform signal enhancement function such as filtering and smoothing for optimization in conventional biometric systems. A handwritten signature is a 1D Daubechies wavelet signal (db4) that utilizes Discrete Wavelet Transform (DWT) and Discrete Cosine Transform (DCT) collectively to create a feature dataset with d-dimensional space. In the proposed work the statistical features characteristics are extracted from each particular signature per data source. Two databases called Signature Verification Competition (SVC) 2004 database and SUBCORPUS 100 MCYT Bimodal database are used to cooperate with the design algorithm. Furthermore dimension reduction technique is applied to the large feature vectors. A system model is trained and evaluated using the support vector machine (SVM) classifier algorithm. Hence an equal error rate (EER) of 8.7 percent and an average correct verification rate of 91.3 percent

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arXiv2018

Smart GSM Based Home Automation System

This research work investigates the potential of Full Home Control, which is the aim of the Home Automation Systems in near future. The analysis and implementation of the home automation technology using Global System for Mobile Communication (GSM) modem to control home appliances such as light, conditional system, and security system via Short Message Service (SMS) text messages is presented in this paper. The proposed research work is focused on the functionality of the GSM protocol, which allows the user to control the target system away from residential using the frequency bandwidths. The concept of serial communication and AT-commands has been applied towards the development of the smart GSM-based home automation system. Homeowners will be able to receive feedback status of any home appliances under control whether switched on or off remotely from their mobile phones. PIC16F887 microcontroller with the integration of GSM provides the smart automated house system with the desired baud rate of 9600 bps. The proposed prototype of GSM based home automation system was implemented and tested with a maximum of four loads and shows the accuracy of greater or equal 98%.

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arXiv2018

Adaptive Intelligent Spider Robot

This paper presents the development of an adaptive intelligent spider robot. With the incorporation of sensors, the four-legged spider robot is able to monitor the environment wirelessly. A new auto-station adaptation National Instrument (NI) controller in the application for an intelligent robot is proposed. The research work will solve the weak adaptive ability of conventional existing robot. The proposed project proposes a self-adaptive smart spider robot that functions without human interfacing. The proposed design utilizes the control scheme with National Instruments (NI) LabVIEW to produce a smart portable system. Furthermore, the adaptive intelligent spider robot easily adapts to new situations when facing obstacles. The design is carried out using feedback loop schematic LabVIEW interfacing with the smart controller and incorporation of GH-311 Ultrasonic Sensor to detect any obstacle in front of the robot, GH-312 Smoke Sensor which use to detect smoke in the particular area and LM35 Temperature sensor to get the temperature for the surround. The proposed module was designed and implemented using movable wireless Router Module TP-Link TL-MR3420 Router transceiver for device communication. The robot was tested and analyzed showing the system efficiency of above 95%, which is competent in robotic applications

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arXiv2018

On-Chip Implementation of Cascaded Integrator Comb filters (CIC) for DSP applications

This paper presents the design of CIC filters based on a low-pass filter for reducing the sampling rate, also known as decimation process. The targeted application for the filter is in the analog to digital conversion (ADC).The CIC is chosen because of its attractive property of both low power and complexity since it does not require multipliers. Simulink toolbox available in Matlab software is used to design and simulate the functionality of the CIC filter. This paper also shows how sample frequency is decreased by CIC filter and it can be used to give enough stop-band attenuation to prevent aliasing after decimation.

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arXiv2018

FPGA Implementation of pipeline Digit-Slicing Multiplier-Less Radix 2 power of 2 DIF SDF Butterfly for Fourier Transform Structure

The need for wireless communication has driven the communication systems to high performance. However, the main bottleneck that affects the communication capability is the Fast Fourier Transform (FFT), which is the core of most modulators. This paper presents FPGA implementation of pipeline digit-slicing multiplier-less radix 22 DIF (Decimation In Frequency) SDF (single path delay feedback) butterfly for FFT structure. The approach is taken, in order to reduce computation complexity in butterfly multiplier, the digit-slicing multiplier-less technique was utilized in the critical path of pipeline Radix-22 DIF SDF FFT structure. The proposed design focused on the trade-off between the speed and active silicon area for the chip implementation. The multiplier input data was sliced into four blocks each one with four bits to process at the same time in parallel. The new architecture was investigated and simulated with MATLAB software. The Verilog HDL code in Xilinx ISE environment was derived to describe the FFT Butterfly functionality and was downloaded to Virtex II FPGA board. Consequently, the Virtex-II FG456 Proto board was used to implement and test the design on the real hardware. As a result, from the findings, the synthesis report indicates the maximum clock frequency of 555.75 MHz with the total equivalent gate count of 32,146 is a marked and significant improvement over Radix 22 DIF SDF FFT butterfly. In comparison with the conventional butterfly architecture design which can only run at a maximum clock frequency of 200.102 MHz and the conventional multiplier can only run at a maximum clock frequency of 221.140 MHz, the proposed system exhibits better results.

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