arXiv subjects

Ruichen Zhao

Publications and source records attributed to Ruichen Zhao.

9 recordsLinked to original sources

arXiv2022

Gate-based spin readout of hole quantum dots with site-dependent $g-$factors

The rapid progress of hole spin qubits in group IV semiconductors has been driven by their potential for scalability. This is owed to the compatibility with industrial manufacturing standards, as well as the ease of operation and addressability via all-electric drives. However, owing to a strong spin-orbit interaction, these systems present variability and anisotropy in key qubit control parameters such as the Land\'e $g-$factor, requiring careful characterisation for reliable qubit operation. Here, we experimentally investigate a hole double quantum dot in silicon by carrying out spin readout with gate-based reflectometry. We show that characteristic features in the reflected phase signal arising from magneto-spectroscopy convey information on site-dependent $g-$factors in the two dots. Using analytical modeling, we extract the physical parameters of our system and, through numerical calculations, we extend the results to point out the prospect of conveniently extracting information about the local $g-$factors from reflectometry measurements.

cond-mat.mes-hall↗

arXiv2021

Towards merged-element transmons using silicon fins: the FinMET

A merged-element transmon (MET) device, based on silicon (Si) fins, is proposed and the first steps to form such a "FinMET" are demonstrated. This new application of fin technology capitalizes on the anisotropic etch of Si(111) relative to Si(110) to define atomically flat, high aspect ratio Si tunnel barriers with epitaxial superconductor contacts on the parallel side-wall surfaces. This process circumvents the challenges associated with the growth of low-loss insulating barriers on lattice matched superconductors. By implementing low-loss, intrinsic float-zone Si as the barrier material rather than commonly used, potentially lossy AlOx, the FinMET is expected to overcome problems with standard transmons by (1) reducing dielectric losses, (2) minimizing the formation of two-level system spectral features, (3) exhibiting greater control over barrier thickness and qubit frequency spread, especially when combined with commercial fin fabrication and atomic-layer digital etching; (4) potentially reducing the footprint by several orders of magnitude; and (5) allowing scalable fabrication. Here, as a first step to making such a device, the fabrication of Si fin capacitors on Si(110) substrates with shadow-deposited Al electrodes is demonstrated. These fin capacitors are then fabricated into lumped element resonator circuits and probed using low-temperature microwave measurements. Further thinning of silicon junctions towards the tunneling regime will enable the scalable fabrication of FinMET devices based on existing silicon technology, while simultaneously avoiding lossy amorphous dielectrics for the tunnel barriers.

quant-ph↗

arXiv2021

A universal quantum gate set for transmon qubits with strong ZZ interactions

High-fidelity single- and two-qubit gates are essential building blocks for a fault-tolerant quantum computer. While there has been much progress in suppressing single-qubit gate errors in superconducting qubit systems, two-qubit gates still suffer from error rates that are orders of magnitude higher. One limiting factor is the residual ZZ-interaction, which originates from a coupling between computational states and higher-energy states. While this interaction is usually viewed as a nuisance, here we experimentally demonstrate that it can be exploited to produce a universal set of fast single- and two-qubit entangling gates in a coupled transmon qubit system. To implement arbitrary single-qubit rotations, we design a new protocol called the two-axis gate that is based on a three-part composite pulse. It rotates a single qubit independently of the state of the other qubit despite the strong ZZ-coupling. We achieve single-qubit gate fidelities as high as 99.1% from randomized benchmarking measurements. We then demonstrate both a CZ gate and a CNOT gate. Because the system has a strong ZZ-interaction, a CZ gate can be achieved by letting the system freely evolve for a gate time $t_g=53.8$ ns. To design the CNOT gate, we utilize an analytical microwave pulse shape based on the SWIPHT protocol for realizing fast, low-leakage gates. We obtain fidelities of 94.6% and 97.8% for the CNOT and CZ gates respectively from quantum progress tomography.

quant-ph↗

arXiv2020

Epitaxial Al/GaAs/Al tri-layers fabricated using a novel wafer-bonding technique

Epitaxial Al/GaAs/Al structures having controlled thickness of high-quality GaAs and pristine interfaces have been fabricated using a wafer-bonding technique. III-V semiconductor/Al structures are grown by molecular beam epitaxy on III-V semiconductor substrates and bonded to silicon and sapphire. Selective etching is used to remove the III-V substrate followed by surface cleaning and superconductor regrowth, resulting in epitaxial Al/GaAs/Al tri-layers on sapphire or silicon substrates. Structures are characterized with reflection high energy electron diffraction, atomic force microscopy, X-ray photoelectron spectroscopy, transmission electron microscopy, and X-ray diffraction. Applications of these structures to the field of quantum information processing is discussed.

physics.app-ph↗

arXiv2020

Overlap junctions for superconducting quantum electronics and amplifiers

Due to their unique properties as lossless, nonlinear circuit elements, Josephson junctions lie at the heart of superconducting quantum information processing. Previously, we demonstrated a two-layer, submicrometer-scale overlap junction fabrication process suitable for qubits with long coherence times. Here, we extend the overlap junction fabrication process to micrometer-scale junctions. This allows us to fabricate other superconducting quantum devices. For example, we demonstrate an overlap-junction-based Josephson parametric amplifier that uses only 2 layers. This efficient fabrication process yields frequency-tunable devices with negligible insertion loss and a gain of ~ 30 dB. Compared to other processes, the overlap junction allows for fabrication with minimal infrastructure, high yield, and state-of-the-art device performance.

physics.app-ph↗

arXiv2020

Pauli Blockade in Silicon Quantum Dots with Spin-Orbit Control

Quantum computation relies on accurate measurements of qubits not only for reading the output of the calculation, but also to perform error correction. Most proposed scalable silicon architectures utilize Pauli blockade of triplet states for spin-to-charge conversion. In recent experiments, there have been instances when instead of conventional triplet blockade readout, Pauli blockade is sustained only between parallel spin configurations, with $|T_0\rangle$ relaxing quickly to the singlet state and leaving $|T_+\rangle$ and $|T_-\rangle$ states blockaded -- which we call \textit{parity readout}. Both types of blockade can be used for readout in quantum computing, but it is crucial to maximize the fidelity and understand in which regime the system operates. We devise and perform an experiment in which the crossover between parity and singlet-triplet readout can be identified by investigating the underlying physics of the $|T_0\rangle$ relaxation rate. This rate is tunable over four orders of magnitude by controlling the Zeeman energy difference between the dots induced by spin-orbit coupling, which in turn depends on the direction of the applied magnetic field. We suggest a theoretical model incorporating charge noise and relaxation effects that explains quantitatively our results. Investigating the model both analytically and numerically, we identify strategies to obtain on-demand either singlet-triplet or parity readout consistently across large arrays of dots. We also discuss how parity readout can be used to perform full two-qubit state tomography and its impact on quantum error detection schemes in large-scale silicon quantum computers.

quant-ph↗

arXiv2019

Superconducting charge sensor coupled to an electron layer in silicon

Schemes aimed at transferring individual electrons in semiconductor devices and detecting possible transfer errors have increasing importance for metrological applications. We study the coupling of a superconducting Josephson-junction-based charge detector to an electron island defined by field-effect in silicon. The flexibility of our device allows one to tune the coupling using the detector as an additional gate electrode. We study the reliability of the electron sensor in different device configurations and the suitability of various operation modes for error detection in electron pumping experiments. As a result, we obtain a charge detection bandwidth of 5.87 kHz with unity signal to noise ratio at 300 mK bath temperature.

cond-mat.mes-hall↗

arXiv2019

Waiting time distributions in a two-level fluctuator coupled to a superconducting charge detector

We analyze charge fluctuations in a parasitic state strongly coupled to a superconducting Josephson-junction-based charge detector. The charge dynamics of the state resembles that of electron transport in a quantum dot with two charge states, and hence we refer to it as a two-level fluctuator. By constructing the distribution of waiting times from the measured detector signal and comparing it with a waiting time theory, we extract the electron in- and out-tunneling rates for the two-level fluctuator, which are severely asymmetric.

cond-mat.mes-hall↗

arXiv2015

A planar Al-Si Schottky Barrier MOSFET operated at cryogenic temperatures

Schottky Barrier (SB)-MOSFET technology offers intriguing possibilities for cryogenic nano-scale devices, such as Si quantum devices and superconducting devices. We present experimental results on a novel device architecture where the gate electrode is self-aligned with the device channel and overlaps the source and drain electrodes. This facilitates a sub-5 nm gap between the source/drain and channel, and no spacers are required. At cryogenic temperatures, such devices function as p-MOS Tunnel FETs, as determined by the Schottky barrier at the Al-Si interface, and as a further advantage, fabrication processes are compatible with both CMOS and superconducting logic technology.

cond-mat.mes-hall↗