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S. D. Cotofana

Publications and source records attributed to S. D. Cotofana.

2 recordsLinked to original sources

Integrated magnonic half-adder

Spin waves and their quanta magnons open up a promising branch of high-speed and low-power information processing. Several important milestones were achieved recently in the realization of separate magnonic data processing units including logic gates, a magnon transistor and units for non-Boolean computing. Nevertheless, the realization of an integrated magnonic circuit consisting of at least two logic gates and suitable for further integration is still an unresolved challenge. Here we demonstrate such an integrated circuit numerically on the example of a magnonic half-adder. Its key element is a nonlinear directional coupler serving as combined XOR and AND logic gate that utilizes the dependence of the spin wave dispersion on its amplitude. The circuit constitutes of only three planar nano-waveguides and processes all information within the magnon domain. Benchmarking of the proposed device is performed showing the potential for sub-aJ energy consumption per operation.

physics.app-ph↗

Compositional Memory Systems for Multimedia Communicating Tasks

Conventional cache models are not suited for real-time parallel processing because tasks may flush each other's data out of the cache in an unpredictable manner. In this way the system is not compositional so the overall performance is difficult to predict and the integration of new tasks expensive. This paper proposes a new method that imposes compositionality to the system?s performance and makes different memory hierarchy optimizations possible for multimedia communicating tasks when running on embedded multiprocessor architectures. The method is based on a cache allocation strategy that assigns sets of the unified cache exclusively to tasks and to the communication buffers. We also analytically formulate the problem and describe a method to compute the cache partitioning ratio for optimizing the throughput and the consumed power. When applied to a multiprocessor with memory hierarchy our technique delivers also performance gain. Compared to the shared cache case, for an application consisting of two jpeg decoders and one edge detection algorithm 5 times less misses are experienced and for an mpeg2 decoder 6.5 times less misses are experienced.

cs.AR↗