S. Gomès | Searcharxiv

arXiv2026

Influence of electrical properties on thermal boundary conductance at metal/semiconductor interface

Recent experimental investigations have demonstrated that doping a semiconductor is a route to increase the thermal boundary conductance at metal/semiconductor interfaces. In this work, the influence of the electrical properties on heat transfer across metal/doped semiconductor junctions is investigated. Specifically, thermal boundary conductance at the interfaces between p- and n-doped silicon and titanium is measured by employing frequency-domain photothermal radiometry under varying external conditions. The influence of the doping level of the semiconductor, the barrier height, and the space charge area is analyzed. In particular, a 40% increase in the interface thermal conductance with the application of a current at n-doped silicon/titanium interfaces is reported. The enhancement of the thermal boundary conductance is explained by the shrinking of the surface charga area induced by the electric current. This study opens the way to modulating interfacial heat transfer at metal/semiconductor interfaces through fine tuning of electrical effects.

cond-mat.mes-hall↗

arXiv2007

Temperature measurement of sub-micrometric ICs by scanning thermal microscopy

Surface temperature measurements were performed with a Scanning Thermal Microscope mounted with a thermoresistive wire probe of micrometrSurface temperature measurements were performed with a Scanning Thermal Microscope mounted with a thermoresistive wire probe of micrometric size. A CMOS device was designed with arrays of resistive lines 0.35$μ$m in width. The array periods are 0.8micron and 10micron to study the spatial resolution of the SThM. Integrated Circuits with passivation layers of micrometric and nanometric thicknesses were tested. To enhance signal-to-noise ratio, the resistive lines were heated with an AC current. The passivation layer of nanometric thickness allows us to distinguish the lines when the array period is 10micron. The results raise the difficulties of the SThM measurement due to the design and the topography of ICs on one hand and the size of the thermal probe on the other hand.ic size. A CMOS device was designed with arrays of resistive lines 0.35$μ$m in width. The array periods are 0.8micron and 10micron to study the spatial resolution of the SThM. Integrated Circuits with passivation layers of micrometric and nanometric thicknesses were tested. To enhance signal-to-noise ratio, the resistive lines were heated with an AC current. The passivation layer of nanometric thickness allows us to distinguish the lines when the array period is 10micron. The results raise the difficulties of the SThM measurement due to the design and the topography of ICs on one hand and the size of the thermal probe on the other hand.

physics.class-ph↗