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S. J. Ben Yoo

Publications and source records attributed to S. J. Ben Yoo.

15 recordsLinked to original sources
arXiv2026

Polarization Tracking and Active Compensation Using Classical Headers in Quantum Wrapper Networking

Quantum wrapper networking (QWN) is an emerging quantum networking protocol that wraps qubits in classical header bits to enable switching/routing, monitoring, and control without detecting the quantum signal. In this work, we encode header bits with two nonorthogonal polarization references to track and actively compensate for the changing birefringence of a 48 km deployed fiber link. Our method is analytical and deterministic, using motorized waveplates and a variable phase retarder to accurately and stably compensate the channel. We verify successful compensation by measuring the polarization stability of single photon qubits and the visibility of entangled photon pairs under both slow birefringence drift due to environmental fluctuations and large sudden changes designed to emulate those that occur during packet switching and rerouting over different fiber paths. For large, sudden changes, our compensator recovers the Stokes vector of single photons to within 10 degrees of the target state on the Poincaré sphere and restores the two-photon interference visibilities to their original levels on the deployed fiber link. Additionally, experiments monitoring long-term compensation over 44 hours show that active polarization compensation maintains the two-photon interference visibility, whereas disabling the compensator leads to visibility degradation over time, particularly in the diagonal-antidiagonal basis, where the average raw visibility decreases by 7.7%. These results add a polarization-control layer to QWN and illustrate that information-carrying headers can enable deterministic physical-layer compensation in the quantum channel over long-distance deployed fiber links.

quant-ph↗
arXiv2025

3D Electronic-Photonic Heterogenous Interconnect Platforms Enabling Energy-Efficient Scalable Architectures For Future HPC Systems

3D interconnects have emerged as a solution to address the scaling issues of interconnect bandwidth and the memory wall problem in high-performance computing (HPC), such as High-Bandwidth Memory (HBM). However, the copper-based electrical interconnect retains fundamental limitations. Dense I/O for high-speed signals lead to degraded signal quality for end-to-end links, necessitating additional circuits to mitigate signal impairments and resulting in poor energy efficiency. We propose a 3D chiplet stacking electronic-photonic interconnect (EPIC) platform, which offers a solution by moving the high-speed data communication interface to the optical domain across the 3D stack by using Through Silicon Optical Vias (TSOV), while retaining the functionality of electrical TSVs and 2.5D interconnects for power delivery and short-reach low-latency communications. We then benchmark the proposed model against state-of-the-art 3D electrical interconnects to demonstrate our 3D EPIC platform beating the 3D electrical interconnects to $>$10 TB/s/$mm^2$ bandwidth density. We present a pathway to extend our demonstrated, industry-ready design to achieving $\leq$100 fJ/bit high-speed communication.

eess.SY↗
arXiv2025

Mixed Precision Photonic Computing with 3D Electronic-Photonic Integrated Circuits

We propose advancing photonic in-memory computing through three-dimensional photonic-electronic integrated circuits using phase-change materials (PCM) and AlGaAs-CMOS technology. These circuits offer high precision (greater than 12 bits), scalability (greater than 1024 by 1024), and massive parallelism (greater than 1 million operations) across the wavelength, spatial, and temporal domains at ultra-low power (less than 1 watt per PetaOPS). Monolithically integrated hybrid PCM-AlGaAs memory resonators handle coarse-precision iterations (greater than 5-bit most significant bit precision) through reversible PCM phase transitions. Electro-optic memristive tuning enables fine-precision updates (greater than 8-bit least significant bit precision), resulting in over 12-bit precision for in-memory computing. The use of low-loss PCM (less than 0.01 dB per cm) and electro-optical tuning yields memristive optical resonators with high Q-factors (greater than 1 million), low insertion loss, and low tuning power. A W by W photonic tensor core composed of PCM-AlGaAs memresonators performs general matrix multiplication (GEMM) across W wavelengths from optical frequency combs, with minimal crosstalk and loss. Hierarchical scaling in the wavelength domain (K) and spatial domain (L) enables this system to address high-dimensional (N) scientific partial differential equation (PDE) problems in a single constant-time operation, compared to the conventional quadratic-time (N squared) computational complexity.

physics.optics↗
arXiv2024

TEGRA -- Scaling Up Terascale Graph Processing with Disaggregated Computing

Graphs are essential for representing relationships in various domains, driving modern AI applications such as graph analytics and neural networks across science, engineering, cybersecurity, transportation, and economics. However, the size of modern graphs are rapidly expanding, posing challenges for traditional CPUs and GPUs in meeting real-time processing demands. As a result, hardware accelerators for graph processing have been proposed. However, the largest graphs that can be handled by these systems is still modest often targeting Twitter graph(1.4B edges approximately). This paper aims to address this limitation by developing a graph accelerator capable of terascale graph processing. Scale out architectures, architectures where nodes are replicated to expand to larger datasets, are natural for handling larger graphs. We argue that this approach is not appropriate for very large-scale graphs because it leads to under utilization of both memory resources and compute resources. Additionally, vertex and edge processing have different access patterns. Communication overheads also pose further challenges in designing scalable architectures. To overcome these issues, this paper proposes TEGRA, a scale-up architecture for terascale graph processing. TEGRA leverages a composable computing system with disaggregated resources and a communication architecture inspired by Active Messages. By employing direct communication between cores and optimizing memory interconnect utilization, TEGRA effectively reduces communication overhead and improves resource utilization, therefore enabling efficient processing of terascale graphs.

cs.ET↗
arXiv2024

Towards Reverse-Engineering the Brain: Brain-Derived Neuromorphic Computing Approach with Photonic, Electronic, and Ionic Dynamicity in 3D integrated circuits

The human brain has immense learning capabilities at extreme energy efficiencies and scale that no artificial system has been able to match. For decades, reverse engineering the brain has been one of the top priorities of science and technology research. Despite numerous efforts, conventional electronics-based methods have failed to match the scalability, energy efficiency, and self-supervised learning capabilities of the human brain. On the other hand, very recent progress in the development of new generations of photonic and electronic memristive materials, device technologies, and 3D electronic-photonic integrated circuits (3D EPIC ) promise to realize new brain-derived neuromorphic systems with comparable connectivity, density, energy-efficiency, and scalability. When combined with bio-realistic learning algorithms and architectures, it may be possible to realize an 'artificial brain' prototype with general self-learning capabilities. This paper argues the possibility of reverse-engineering the brain through architecting a prototype of a brain-derived neuromorphic computing system consisting of artificial electronic, ionic, photonic materials, devices, and circuits with dynamicity resembling the bio-plausible molecular, neuro/synaptic, neuro-circuit, and multi-structural hierarchical macro-circuits of the brain based on well-tested computational models. We further argue the importance of bio-plausible local learning algorithms applicable to the neuromorphic computing system that capture the flexible and adaptive unsupervised and self-supervised learning mechanisms central to human intelligence. Most importantly, we emphasize that the unique capabilities in brain-derived neuromorphic computing prototype systems will enable us to understand links between specific neuronal and network-level properties with system-level functioning and behavior.

cs.ET↗
arXiv2023

Demonstration of Programmable Brain-Inspired Optoelectronic Neuron in Photonic Spiking Neural Network with Neural Heterogeneity

Photonic Spiking Neural Networks (PSNN) composed of the co-integrated CMOS and photonic elements can offer low loss, low power, highly-parallel, and high-throughput computing for brain-inspired neuromorphic systems. In addition, heterogeneity of neuron dynamics can also bring greater diversity and expressivity to brain-inspired networks, potentially allowing for the implementation of complex functions with fewer neurons. In this paper, we design, fabricate, and experimentally demonstrate an optoelectronic spiking neuron that can simultaneously achieve high programmability for heterogeneous biological neural networks and maintain high-speed computing. We demonstrate that our neuron can be programmed to tune four essential parameters of neuron dynamics under 1GSpike/s input spiking pattern signals. A single neuron circuit can be tuned to output three spiking patterns, including chattering behaviors. The PSNN consisting of the optoelectronic spiking neuron and a Mach-Zehnder interferometer (MZI) mesh synaptic network achieves 89.3% accuracy on the Iris dataset. Our neuron power consumption is 1.18 pJ/spike output, mainly limited by the power efficiency of the vertical-cavity-lasers, optical coupling efficiency, and the 45 nm CMOS platform used in this experiment, and is predicted to achieve 36.84 fJ/spike output with a 7 nm CMOS platform (e.g. ASAP7) integrated with silicon photonics containing on-chip micron-scale lasers.

eess.SY↗
arXiv2023

Programmable Integrated Photonics for Topological Hamiltonians

A variety of topological Hamiltonians have been demonstrated in photonic platforms, leading to fundamental discoveries and enhanced robustness in applications such as lasing, sensing, and quantum technologies. To date, each topological photonic platform implements a specific type of Hamiltonian with inexistent or limited reconfigurability. Here, we propose and demonstrate different topological models by using the same reprogrammable integrated photonics platform, consisting of a hexagonal mesh of silicon Mach-Zehnder interferometers with phase-shifters. We specifically demonstrate a one-dimensional Su-Schrieffer-Heeger Hamiltonian supporting a localized topological edge mode and a higher-order topological insulator based on a two-dimensional breathing Kagome Hamiltonian with three corner states. These results highlight a nearly universal platform for topological models that may fast-track research progress toward applications of topological photonics and other coupled systems.

physics.optics↗
arXiv2023

Quantum Wrapper Networking

We introduce a new concept of Quantum Wrapper Networking, which enables control, management, and operation of quantum networks that can co-exist with classical networks while keeping the requirements for quantum networks intact. The quantum wrapper networks (QWNs) enable the transparent and interoperable transportation of quantum wrapper datagrams consisting of quantum payloads and, notably, classical headers to facilitate the datagram switching without measuring or disturbing the qubits of the quantum payload. Furthermore, QWNs can utilize the common network control and management for performance monitoring on the classical header and infer the quantum channel quality.

quant-ph↗
arXiv2022

Scalable Nanophotonic-Electronic Spiking Neural Networks

Spiking neural networks (SNN) provide a new computational paradigm capable of highly parallelized, real-time processing. Photonic devices are ideal for the design of high-bandwidth, parallel architectures matching the SNN computational paradigm. Co-integration of CMOS and photonic elements allow low-loss photonic devices to be combined with analog electronics for greater flexibility of nonlinear computational elements. As such, we designed and simulated an optoelectronic spiking neuron circuit on a monolithic silicon photonics (SiPh) process that replicates useful spiking behaviors beyond the leaky integrate-and-fire (LIF). Additionally, we explored two learning algorithms with the potential for on-chip learning using Mach-Zehnder Interferometric (MZI) meshes as synaptic interconnects. A variation of Random Backpropagation (RPB) was experimentally demonstrated on-chip and matched the performance of a standard linear regression on a simple classification task. Meanwhile, the Contrastive Hebbian Learning (CHL) rule was applied to a simulated neural network composed of MZI meshes for a random input-output mapping task. The CHL-trained MZI network performed better than random guessing but does not match the performance of the ideal neural network (without the constraints imposed by the MZI meshes). Through these efforts, we demonstrate that co-integrated CMOS and SiPh technologies are well-suited to the design of scalable SNN computing architectures.

cs.NE↗
arXiv2021

Izhikevich-Inspired Optoelectronic Neurons with Excitatory and Inhibitory Inputs for Energy-Efficient Photonic Spiking Neural Networks

We designed, prototyped, and experimentally demonstrated, for the first time to our knowledge, an optoelectronic spiking neuron inspired by the Izhikevich model incorporating both excitatory and inhibitory optical spiking inputs and producing optical spiking outputs accordingly. The optoelectronic neurons consist of three transistors acting as electrical spiking circuits, a vertical-cavity surface-emitting laser (VCSEL) for optical spiking outputs, and two photodetectors for excitatory and inhibitory optical spiking inputs. Additional inclusion of capacitors and resistors complete the Izhikevich-inspired optoelectronic neurons, which receive excitatory and inhibitory optical spikes as inputs from other optoelectronic neurons. We developed a detailed optoelectronic neuron model in Verilog-A and simulated the circuit-level operation of various cases with excitatory input and inhibitory input signals. The experimental results closely resemble the simulated results and demonstrate how the excitatory inputs trigger the optical spiking outputs while the inhibitory inputs suppress the outputs. Utilizing the simulated neuron model, we conducted simulations using fully connected (FC) and convolutional neural networks (CNN). The simulation results using MNIST handwritten digits recognition show 90% accuracy on unsupervised learning and 97% accuracy on a supervised modified FC neural network. We further designed a nanoscale optoelectronic neuron utilizing quantum impedance conversion where a 200 aJ/spike input can trigger the output from on-chip nanolasers with 10 fJ/spike. The nanoscale neuron can support a fanout of ~80 or overcome 19 dB excess optical loss while running at 10 GSpikes/second in the neural network, which corresponds to 100x throughput and 1000x energy-efficiency improvement compared to state-of-art electrical neuromorphic hardware such as Loihi and NeuroGrid.

cs.NE↗
arXiv2019

DeepRMSA: A Deep Reinforcement Learning Framework for Routing, Modulation and Spectrum Assignment in Elastic Optical Networks

This paper proposes DeepRMSA, a deep reinforcement learning framework for routing, modulation and spectrum assignment (RMSA) in elastic optical networks (EONs). DeepRMSA learns the correct online RMSA policies by parameterizing the policies with deep neural networks (DNNs) that can sense complex EON states. The DNNs are trained with experiences of dynamic lightpath provisioning. We first modify the asynchronous advantage actor-critic algorithm and present an episode-based training mechanism for DeepRMSA, namely, DeepRMSA-EP. DeepRMSA-EP divides the dynamic provisioning process into multiple episodes (each containing the servicing of a fixed number of lightpath requests) and performs training by the end of each episode. The optimization target of DeepRMSA-EP at each step of servicing a request is to maximize the cumulative reward within the rest of the episode. Thus, we obviate the need for estimating the rewards related to unknown future states. To overcome the instability issue in the training of DeepRMSA-EP due to the oscillations of cumulative rewards, we further propose a window-based flexible training mechanism, i.e., DeepRMSA-FLX. DeepRMSA-FLX attempts to smooth out the oscillations by defining the optimization scope at each step as a sliding window, and ensuring that the cumulative rewards always include rewards from a fixed number of requests. Evaluations with the two sample topologies show that DeepRMSA-FLX can effectively stabilize the training while achieving blocking probability reductions of more than 20.3% and 14.3%, when compared with the baselines.

cs.NI↗