arXiv subjects

Saber Ganjisaffar

Publications and source records attributed to Saber Ganjisaffar.

3 recordsLinked to original sources

arXiv2026

Microflow: Microarchitectural Causal Observability for Deep Cross-Layer Analysis and Optimization

Modern computer architecture relies heavily on simulation to identify bottlenecks and evaluate optimizations. However, existing microarchitectural performance analysis methods are fundamentally limited by an instruction-centric paradigm that captures only downstream symptoms while leaving the true microarchitectural root cause opaque. Because modern processors are governed by complex interactions across non-instruction entities like prefetchers, replacement policies, and shared queue occupancies, instruction-centric frameworks miss the mechanisms that dictate performance. To eliminate this blind spot, we present Microflow, a framework that achieves causal observability in microarchitectural simulation. To address this, we introduce the Microflow intermediate representation (MFIR), which models execution through microarchitecture-tailored core abstractions such as flows, resource tenancies, and causal edges. By compiling simulation runs into a relational causal database, Microflow decouples tracing from analytical processing. This transforms complex diagnostics into expressive queries, enabling architects to trace performance symptoms directly to hardware root causes without developing bespoke analysis scripts or running costly re-simulations for every new question. We demonstrate that Microflow solves pathologies opaque to conventional tools. Across CVP-1 benchmarks, Microflow decomposes a 22% prefetcher oracle headroom by attributing 61.4% of stall mass to specific hardware prefetcher decisions, yielding a 2.31% average speedup (peaking at 25.11%). Furthermore, it exposes the hidden pipeline-blocking residue of wrong-path execution with high portability and precision across simulators.

cs.AR↗

arXiv2025

ShadowScope: GPU Monitoring and Validation via Composable Side Channel Signals

As modern systems increasingly rely on GPUs for computationally intensive tasks such as machine learning acceleration, ensuring the integrity of GPU computation has become critically important. Recent studies have shown that GPU kernels are vulnerable to both traditional memory safety issues (e.g., buffer overflow attacks) and emerging microarchitectural threats (e.g., Rowhammer attacks), many of which manifest as anomalous execution behaviors observable through side-channel signals. However, existing golden model based validation approaches that rely on such signals are fragile, highly sensitive to interference, and do not scale well across GPU workloads with diverse scheduling behaviors. To address these challenges, we propose ShadowScope, a monitoring and validation framework that leverages a composable golden model. Instead of building a single monolithic reference, ShadowScope decomposes trusted kernel execution into modular, repeatable functions that encode key behavioral features. This composable design captures execution patterns at finer granularity, enabling robust validation that is resilient to noise, workload variation, and interference across GPU workloads. To further reduce reliance on noisy software-only monitoring, we introduce ShadowScope+, a hardware-assisted validation mechanism that integrates lightweight on-chip checks into the GPU pipeline. ShadowScope+ achieves high validation accuracy with an average runtime overhead of just 4.6%, while incurring minimal hardware and design complexity. Together, these contributions demonstrate that side-channel observability can be systematically repurposed into a practical defense for GPU kernel integrity.

cs.CR↗

arXiv2025

PRACtical: Subarray-Level Counter Update and Bank-Level Recovery Isolation for Efficient PRAC Rowhammer Mitigation

As DRAM density increases, Rowhammer becomes more severe due to heightened charge leakage, reducing the number of activations needed to induce bit flips. The DDR5 standard addresses this threat with in-DRAM per-row activation counters (PRAC) and the Alert Back-Off (ABO) signal to trigger mitigation. However, PRAC adds performance overhead by incrementing counters during the precharge phase, and recovery refreshes stalls the entire memory channel, even if only one bank is under attack. We propose PRACtical, a performance-optimized approach to PRAC+ABO that maintains the same security guarantees. First, we reduce counter update latency by introducing a centralized increment circuit, enabling overlap between counter updates and subsequent row activations in other subarrays. Second, we enhance the $RFM_{ab}$ mitigation by enabling bank-level granularity: instead of stalling the entire channel, only affected banks are paused. This is achieved through a DRAM-resident register that identifies attacked banks. PRACtical improves performance by 8% on average (up to 20%) over the state-of-the-art, reduces energy by 19%, and limits performance degradation from aggressive performance attacks to less than 6%, all while preserving Rowhammer protection.

cs.AR↗