arXiv subjects

Sachin S. Sapatnekar

Publications and source records attributed to Sachin S. Sapatnekar.

41 records · Page 3Linked to original sources

arXiv2019

PIMBALL: Binary Neural Networks in Spintronic Memory

Neural networks span a wide range of applications of industrial and commercial significance. Binary neural networks (BNN) are particularly effective in trading accuracy for performance, energy efficiency or hardware/software complexity. Here, we introduce a spintronic, re-configurable in-memory BNN accelerator, PIMBALL: Processing In Memory BNN AcceL(L)erator, which allows for massively parallel and energy efficient computation. PIMBALL is capable of being used as a standard spintronic memory (STT-MRAM) array and a computational substrate simultaneously. We evaluate PIMBALL using multiple image classifiers and a genomics kernel. Our simulation results show that PIMBALL is more energy efficient than alternative CPU, GPU, and FPGA based implementations while delivering higher throughput.

cs.ET↗

arXiv2018

SkyLogic - A proposal for a skyrmion logic device

This work proposes a novel logic device (SkyLogic) based on skyrmions, which are magnetic vortex-like structures that have low depinning current density and are robust to defects. A charge current sent through a polarizer ferromagnet (P-FM) nucleates a skyrmion at the input end of an intra-gate FM interconnect with perpendicular magnetic anisotropy (PMA-FM). The output end of the PMA--FM forms the free layer of an MTJ stack. A spin Hall metal (SHM) is placed beneath the PMA-FM. The skyrmion is propagated to the output end of the PMA-FM by passing a charge current through the SHM. The resistance of the MTJ stack is low (high) when a skyrmion is present (absent) in the free layer, thereby realizing an inverter. A framework is developed to analyze the performance of the SkyLogic device. A circuit-level technique is developed that counters the transverse displacement of skyrmion in the PMA-FM and allows use of high current densities for fast propagation. The design space exploration of the PMA-FM material parameters is performed to obtain an optimal design point. At the optimal point, we obtain an inverter delay of 434 ps with a switching energy of 7.1 fJ.

cs.ET↗

arXiv2017

CoMET: Composite-Input Magnetoelectric-based Logic Technology

This work proposes CoMET, a fast and energy-efficient spintronics device for logic applications. An input voltage is applied to a ferroelectric (FE) material, in contact with a composite structure - a ferromagnet (FM) with in-plane magnetic anisotropy (IMA) placed on top of an intra-gate FM interconnect with perpendicular magnetic anisotropy (PMA). Through the magnetoelectric (ME) effect, the input voltage nucleates a domain wall (DW) at the input end of the PMA-FM interconnect. An applied current then rapidly propagates the DW towards the output FE structure, where the inverse-ME effect generates an output voltage. This voltage is propagated to the input of the next CoMET device using a novel circuit structure that enables efficient device cascading. The material parameters for CoMET are optimized by systematically exploring the impact of parameter choices on device performance. Simulations on a 7nm CoMET device show fast, low-energy operation, with a delay/energy of 98ps/68aJ for INV and 135ps/85aJ for MAJ3.

cs.ET↗

arXiv2017

STEM: A Scheme for Two-phase Evaluation of Majority Logic

The switching time of a magnet in a spin current based majority gate depends on the input vector combination, and this often restricts the speed of majority-based circuits. To address this issue, this work proposes a novel two-phase scheme to implement majority logic and evaluates it on an all-spin logic (ASL) majority-based logic structures. In Phase 1, the output is initialized to a preset value. Next in Phase 2, the inputs are evaluated to switch the output magnet to its correct value. The time window for the output to switch in Phase 2 is fixed. Using such a scheme, an n-input AND gate which requires a total of (2n-1) inputs in the conventional implementation can now be implemented with only (n+1) inputs. When applied to standard logic functions, it is demonstrated that the proposed method of designing ASL gates are 1.6-3.4X faster and 1.9-6.9X more energy-efficient than the conventional method, and for a five-magnet full adder, it is shown that the proposed ASL implementation is 1.5X faster, 2.2X more energy-efficient, and provides a 16% improvement in area.

cs.ET↗

arXiv2006

Stochastic Preconditioning for Iterative Linear Equation Solvers

This paper presents a new stochastic preconditioning approach. For symmetric diagonally-dominant M-matrices, we prove that an incomplete LDL factorization can be obtained from random walks, and used as a preconditioner for an iterative solver, e.g., conjugate gradient. It is argued that our factor matrices have better quality, i.e., better accuracy-size tradeoffs, than preconditioners produced by existing incomplete factorization methods. Therefore the resulting preconditioned conjugate gradient (PCG) method requires less computation than traditional PCG methods to solve a set of linear equations with the same error tolerance, and the advantage increases for larger and denser sets of linear equations. These claims are verified by numerical tests, and we provide techniques that can potentially extend the theory to more general types of matrices.

math.NA↗