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Samo Gerkšič

Publications and source records attributed to Samo Gerkšič.

2 recordsLinked to original sources

Finite-word-length FPGA implementation of model predictive control for ITER resistive wall mode control

In advanced tokamak scenarios, active feedback control of unstable resistive wall modes (RWM) may be required. A RWM is an instability due to plasma kink at higher plasma pressure, moderated by the presence of a resistive wall surrounding the plasma. We address the dominant kink instability associated with the main nonaxisymmetric (n = 1) RWM, described by the CarMa model. Model predictive control (MPC) is used, with the aim of enlarging the domain of attraction of the unstable RWM modes subject to power-supply voltage constraints. The implementation of MPC is challenging, because the related quadratic programming (QP) on-line optimization problems must be solved at a sub-ms sampling rate. Using complexity-reduction pre-processing techniques and a primal fast gradient method (FGM) QP solver, sufficiently short computation times for ITER are reachable using a standard personal computer (PC). In this work we explore even faster finite-word-length (FWL) implementation using field-programmable gate arrays (FPGA), which would facilitate experimental testing of such control algorithms on dynamically faster medium-sized tokamaks, and compare the computational accuracy and time with the PC implementation.

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FPGA acceleration of Model Predictive Control for Iter Plasma current and shape control

A faster implementation of the Quadratic Programming (QP) solver used in the Model Predictive Control scheme for Iter Plasma current and shape control was developed for Xilinx Field-Programmable Gate Array (FPGA) platforms using a high-level synthesis approach. The QP solver is based on the dual Fast Gradient Method (dFGM). The dFGM is essentially an iterative algorithm, where matrix-vector arithmetic operations within the main iteration loop may be parallelized. This type of parallelism is not well-suited to standard multi-core processors because the number of operations to be spread among processing threads is relatively small considering the time-scale of thread scheduling. The FPGA implementation avoids this issue, but it requires specific techniques of code optimization in order to achieve faster solver execution.

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