arXiv subjects

Sandeep Chandran

Publications and source records attributed to Sandeep Chandran.

3 recordsLinked to original sources

arXiv2026

Dynamically Reprogrammable Runtime Monitors for Bounded-time MTL

A Runtime Verification (RV) framework that supports online, at-speed verification of properties that can change dynamically (during in-field operations) will benefit a large variety of applications. Several state-of-the-art RV frameworks propose to implement monitors on FPGAs. While this approach can support changes to the property being monitored during in-field operations, they struggle to keep pace with the system under verification which use high-performance processors. In this work, we propose a novel, reprogrammable monitor that is implemented using standard cells instead of FPGAs. This allows the monitor to be co-located with the system under verification (on the same die), and hence is amenable to at-speed monitoring of properties. Our proposed design consists of a programmable unit that implements five basic operations and a set of queue-update rules. We show that a composition of such programmable units faithfully implements discrete time, bounded MTL. We demonstrate through simulations that our proposed monitor can be reprogrammed (through its I/O pins) post deployment. A fairly large monitor which can support MTL formulae upto 16 atomic propositions occupies only 0.55 mm^2, while operating at a frequency of 1.25 GHz.

cs.LO↗

arXiv2023

Dynamic Ineffectuality-based Clustered Architectures

The direction of conditional branches is predicted correctly in modern processors with great accuracy. We find several instructions in the dynamic instruction stream that contribute only towards computing the condition of these instructions. Hence, when the predicted direction of conditional branches is indeed correct, these instructions become Ineffectual - the functional state of the program would not be different had these instructions been dropped. However, the execution of ineffectual instructions cannot be avoided altogether because it is possible that the prediction of the branch direction is wrong. In this work, we determine all sources of ineffectuality in an instruction stream such as conditional branches, predicated instructions, indirect jumps and dynamically dead instructions. Then, we propose a technique to steer the ineffectual instructions away from the primary execution cluster so that effectual instructions can execute uncontended. We find that such ineffectuality-based clustering of instructions naturally simplifies the design and avoids several caveats of a clustered architecture. Finally, we propose a technique to detect instances when instructions were incorrectly marked as ineffectual, say due to a branch misprediction, and recover the pipeline. The empirical evaluation of the proposed changes on the SPEC CPU2017 and GAPBS benchmarks show performance uplifts of up to 4.9% and 10.3% on average respectively.

cs.AR↗

arXiv2015

Fundamental Results for a Generic Implementation of Barriers using Optical Interconnects

In this report, we report some fundamental results and bounds on the number of messages and storage required to implement barriers using futuristic on-chip optical and RF networks. We prove that it is necessary to maintain a count to at least N (number of threads) in memory, broadcast the barrier id at least once, and if we elect a co-ordinator, we can reduce the number of messages by a factor of O(N ).

cs.DC↗