arXiv subjects

Sanghyun Kang

Publications and source records attributed to Sanghyun Kang.

5 recordsLinked to original sources

arXiv2026

Experiments and Modeling of Defect Dynamics and BTI Behavior in Doped InO TFTs during $400^\circ$C Post-Processing Forming Gas Annealing

We investigate the impact of a monolithic three-dimensional (M3D) integration process-critical $400^\circ$C post-processing forming gas anneal (FGA) on the electrical performance, reliability, and defect evolution of oxide-channel thin-film transistors (TFTs), combining systematic experiments with density-functional-theory (DFT)-based liquid-quench molecular-dynamics (MD) simulations. Indium tungsten oxide (IWO) TFTs are employed as a model system and encapsulated with a thin 3 nm Al$_2$O$_3$ / 3 nm HfO$_2$ hybrid layer that effectively suppresses external hydrogen ingress. We reveal a non-monotonic evolution of device behavior during FGA, governed by initial densification followed by partial crystallization. Short-duration FGA (10 min) induces channel densification and the formation of shallow, delocalized defect states, leading to pronounced positive bias temperature instability (PBTI) degradation and the emergence of a characteristic transfer-curve "kink." With prolonged annealing (>40 min), partial crystallization of the oxide channel occurs, stabilizing hydrogen in deep, localized defect states, suppressing hydrogen mobility, and restoring device reliability. As a result, the PBTI shift is reduced to 10.4 mV after 2000 seconds of stress, accompanied by complete elimination of the transfer-curve kink. These findings provide a mechanistic understanding of hydrogen-defect interactions during high-temperature post-processing FGA and demonstrate that appropriate hydrogen-blocking encapsulation enables oxide-channel TFT integration without compromising electrical performance or reliability.

cond-mat.mtrl-sci↗

arXiv2026

SplitAdapter: Load-Aware Humanoid Loco-Manipulation via Factorized Adaptation

Humanoid loco-manipulation requires stable whole-body control under varying object masses and pickup/placement heights. This becomes particularly challenging in sim-to-real transfer, where object-induced load variation and robot-side dynamics mismatch interact during physical contact. Existing history-based adapters often compress these factors into a single latent representation, which can weaken robustness under heavy-load manipulation. We propose \textbf{SplitAdapter: Load-Aware Humanoid Loco-Manipulation via Factorized Adaptation}, which freezes a pretrained box manipulation policy and extends it with object/load and dynamics-aware context encoders trained with split world-model objectives, GRL-based cross-adversarial regularization, and hierarchical Feature-wise Linear Modulation (FiLM). In sim-to-sim experiments and real-world deployment, SplitAdapter improves Full-task success over the base policy and world-model FiLM baselines across object masses of $2$, $4$, and $6$ kg and pickup/placement heights of $0$, $30$, and $60$ cm, with the largest improvements under heavy-load conditions.

cs.RO↗

arXiv2026

Engineering Wake-Up-Free Ferroelectric Capacitors with Enhanced High-Temperature Reliability

We systematically explore the design space of ferroelectric hafnium-zirconium oxide (H0.5Z0.5O or HZO) heterostructures for reliable high temperature operation. HZO films are deposited using thermal and plasma-enhanced atomic layer deposition (Th-ALD and PE-ALD) on tungsten (W) and titanium nitride (TiN) bottom electrodes (BE), while maintaining identical top electrodes. We demonstrate that PE-ALD HZO capacitors integrated with W BE exhibit wake-up-free switching up to 125C, along with significantly improved endurance compared to Th-ALD HZO/W devices across a wide temperature range (85-125C). By decoupling the contributions of the plasma-deposited HZO film and the oxidized bottom interface inherently formed during PE-ALD, we identify the oxidized W interfacial layer (WOx) as the primary factor governing endurance enhancement and wake-up suppression at elevated temperatures, while the PE-ALD HZO film provides secondary benefits in reducing wake-up. In contrast, PE-ALD HZO capacitors fabricated on TiN BE show no substantial improvement in wake-up behavior or endurance relative to Th-ALD HZO/TiN devices, despite the formation of an unintentional TiOxNy interfacial layer, and instead exhibit degraded polarization. This difference arises from the significantly weaker endurance enhancement and no wake-up suppression provided by oxidized TiN compared to oxidized W under comparable oxidation conditions. Overall, PE-ALD HZO films enable superior ferroelectric performance at elevated temperatures only when deposited on W BE, while Th-ALD HZO films remain a viable option for high temperature operation on TiN BE. These findings clarify the interplay between deposition technique, electrode chemistry, and interfacial oxidation, and provide design guidelines for integrating ferroelectric memories into monolithic 3D systems under stringent thermal constraints.

cond-mat.mtrl-sci↗

arXiv2026

Sub-nm2 ferroelectric domains via charged 180 degree walls in ZrO2

Flat phonon bands in fluorite ferroelectrics (HfO2 or ZrO2) shrink polar domains laterally to an irreducible half-unit-cell width (0.27 nm) within which the vertical arrangement of dipoles is expected to remain uniform. We report on the direct observation of nonuniform and nearly discrete vertical arrangements of dipoles in ZrO2 thin films consisting of closely spaced head-to-head (HH) and tail-to-tail (TT) charged 180 degree walls, each exhibiting a distinct bulk-like structure. These charged domain walls (CDWs) further compress the irreducibly narrow, laterally stacked domains vertically to a thickness of 1-2.75 nm, yielding in-plane domains with sub-nm2 footprints-among the smallest ever reported for any ferroelectric material. The HH and TT walls form due to their flat longitudinal optical (LO) polar bands and are electrostatically stabilized by bound-charge compensation via interstitial oxygen atoms, which act as natural structural defects at the HH walls. Moreover, these walls are predicted to be conducting and to exhibit ultralow propagation barriers, with HH walls (1.6 meV) being far more mobile than TT walls (22.3 meV), indicating strong potential for low-voltage, domain-wall-based nanoelectronics.

cond-mat.mtrl-sci↗

arXiv2025

Hf/Zr Superlattice-Based High-\k{appa} Gate Dielectrics with Dipole Layer Engineering for Advanced CMOS

Advanced logic transistors require gate dielectrics that achieve sub-nanometer equivalent oxide thickness (EOT), suppress leakage, and satisfy three key requirements: (i) compatibility with RMG-like high-temperature processing, (ii) sufficient Vth tunability for multi-Vth design, and (iii) high device reliability. However, meeting all of these requirements simultaneously has been difficult with conventional high-k systems. In this work, we demonstrate that Hf/Zr-based gate stacks quantitatively satisfy these conditions. After a 700 C N2 anneal, the HZH superlattice achieves an EOT of 7.3 A, lower than conventional HfO2-only stacks (8.5 A) while maintaining comparable leakage. Embedding a 3 A Al2O3 dipole within an HfO2/ZrO2/HfO2 superlattice (HZHA) breaks the conventional dipole trade-off, achieving an EOT of 8.4 A, lower than the 9.0 A of a standard HfO2/Al2O3 stack, while providing a flatband voltage shift greater than 200 mV, thereby enabling multi-Vth tuning without compromising scaling. Furthermore, under -2 V negative-bias temperature stress at 125 C for 100 s, HZHA and HA exhibit comparable flatband voltage drifts of 87 mV and 97 mV, respectively, confirming that strong Vth tunability and sub-nanometer EOT can be achieved without compromising stability. In addition to these quantitative advances, this study reveals previously unreported physical insights into dipole behavior and interfacial diffusion in ultrathin Hf/Zr multilayers. These results establish HZHA as an RMG-compatible, Vth-tunable, low-EOT dielectric platform capable of supporting logic scaling beyond the 1 nm frontier.

cond-mat.mes-hall↗