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Saurabh Raje

Publications and source records attributed to Saurabh Raje.

5 recordsLinked to original sources

CoNST: Code Generator for Sparse Tensor Networks

Sparse tensor networks are commonly used to represent contractions over sparse tensors. Tensor contractions are higher-order analogs of matrix multiplication. Tensor networks arise commonly in many domains of scientific computing and data science. After a transformation into a tree of binary contractions, the network is implemented as a sequence of individual contractions. Several critical aspects must be considered in the generation of efficient code for a contraction tree, including sparse tensor layout mode order, loop fusion to reduce intermediate tensors, and the interdependence of loop order, mode order, and contraction order. We propose CoNST, a novel approach that considers these factors in an integrated manner using a single formulation. Our approach creates a constraint system that encodes these decisions and their interdependence, while aiming to produce reduced-order intermediate tensors via fusion. The constraint system is solved by the Z3 SMT solver and the result is used to create the desired fused loop structure and tensor mode layouts for the entire contraction tree. This structure is lowered to the IR of the TACO compiler, which is then used to generate executable code. Our experimental evaluation demonstrates very significant (sometimes orders of magnitude) performance improvements over current state-of-the-art sparse tensor compiler/library alternatives.

cs.PL

Efficient Scaling of Dynamic Graph Neural Networks

We present distributed algorithms for training dynamic Graph Neural Networks (GNN) on large scale graphs spanning multi-node, multi-GPU systems. To the best of our knowledge, this is the first scaling study on dynamic GNN. We devise mechanisms for reducing the GPU memory usage and identify two execution time bottlenecks: CPU-GPU data transfer; and communication volume. Exploiting properties of dynamic graphs, we design a graph difference-based strategy to significantly reduce the transfer time. We develop a simple, but effective data distribution technique under which the communication volume remains fixed and linear in the input size, for any number of GPUs. Our experiments using billion-size graphs on a system of 128 GPUs shows that: (i) the distribution scheme achieves up to 30x speedup on 128 GPUs; (ii) the graph-difference technique reduces the transfer time by a factor of up to 4.1x and the overall execution time by up to 40%

cs.DC

Kvik: A task based middleware with composable scheduling policies

In this paper we present Kvik: an implementation of a task-based "middleware" for shared memory parallel programming in the Rust language built on top of the Rayon library. We devise a system allowing several task-splitting schedulers to be finely tuned by the end users. Among these, we propose an implementation of an adaptive scheduler reducing tasks creations (splits) to bare minimum by linking tasks splitting to steal requests. Another important scheduler that allows turning computations into sequences of parallel operations is described. This operator proves itself particularly useful for interruptible computations. We exhibit different code examples well suited for different types of schedulers. We conclude our work with a set of benchmarks making heavy use of composability. In particular we present a parallel stable sort implementation with up to 1.5x more speedup when compared to the state-of-the-art parallel sorting implementation.

cs.DC

Development of On Board Computer for a Nanosatellite

This paper describes the process of conceptualization, design, and testing of the Onboard Computer (OBC) Software for a 3U nanosatellite. The on-board computer of the satellite is responsible for initiating dataflow between onboard hardware, performing image compression, and run control algorithms like fine pointing, sun pointing, ground pointing for payload operation and idle state detumbling. The actuation is carried out by interfacing magnetorquers and reaction wheels with the OBC. The software of the onboard computer is implemented on a Linux based operating system run on the ARM Cortex A9 processor which is part of the Zynq-7000 SoC. A Field Programmable Gate Array (FPGA) is used specifically for image compression. The compressed image is stored in a serial flash memory shared between the camera and the FPGA. The architecture comprises of a system-wide I2C bus to which the sensors interfaced. The collected data is used for logging followed by downlink and as input to algorithms used for pointing and detumbling. An SPI interface is used between the Power Subsystem microcontroller and the On-Board Computer since a large amount of housekeeping data will have to be exchanged at high rates. Reaction wheels and magnetorquers are actuated by current driver circuits which get the control signals from the OBC. The satellite is modelled as a Finite State Machine for software development. The states broadly fall under two categories, Normal and Emergency. Each state has a predetermined set of logical tasks to be run, which are abstracted as separate processes in the memory. State transitions take place by polling the health metrics of the satellite. However, hardware interrupts are implemented on selected peripherals which ensure an asynchronous switching to the Emergency States for safety. A review of some common fault detection, isolation and removal methods used shall conclude the paper.

eess.SY

Decentralised firewall for malware detection

This paper describes the design and development of a decentralized firewall system powered by a novel malware detection engine. The firewall is built using blockchain technology. The detection engine aims to classify Portable Executable (PE) files as malicious or benign. File classification is carried out using a deep belief neural network (DBN) as the detection engine. Our approach is to model the files as grayscale images and use the DBN to classify those images into the aforementioned two classes. An extensive data set of 10,000 files is used to train the DBN. Validation is carried out using 4,000 files previously unexposed to the network. The final result of whether to allow or block a file is obtained by arriving at a proof of work based consensus in the blockchain network.

cs.CR