arXiv subjects

Scott Zarr

Publications and source records attributed to Scott Zarr.

4 recordsLinked to original sources

arXiv2023

Extremely Large Area (88 mm X 88 mm) Superconducting Integrated Circuit (ELASIC)

Superconducting integrated circuit (SIC) is a promising "beyond-CMOS" device technology enables speed-of-light, nearly lossless communications to advance cryogenic (4 K or lower) computing. However, the lack of large-area superconducting IC has hindered the development of scalable practical systems. Herein, we describe a novel approach to interconnect 16 high-resolution deep UV (DUV EX4, 248 nm lithography) full reticle circuits to fabricate an extremely large (88mm X 88 mm) area superconducting integrated circuit (ELASIC). The fabrication process starts by interconnecting four high-resolution DUV EX4 (22 mm X 22 mm) full reticles using a single large-field (44 mm X 44 mm) I-line (365 nm lithography) reticle, followed by I-line reticle stitching at the boundaries of 44 mm X 44 mm fields to fabricate the complete ELASIC field (88 mm X 88 mm). The ELASIC demonstrated a 2X-12X reduction in circuit features and maintained high-stitched line superconducting critical currents. We examined quantum flux parametron (QFP) circuits to demonstrate the viability of common active components used for data buffering and transmission. Considering that no stitching requirement for high-resolution EX4 DUV reticles is employed, the present fabrication process has the potential to advance the scaling of superconducting quantum devices.

cond-mat.supr-con↗

arXiv2019

Planarized Fabrication Process With Two Layers of SIS Josephson Junctions and Integration of SIS and SFS π-Junctions

We present our new fabrication Process for Superconductor Electronics (PSE2) that integrates two (2) layers of Josephson junctions in a fully planarized multilayer process on 200-mm wafers. The two junction layers can be, e.g., conventional Superconductor-Insulator-Superconductor (SIS) Nb/Al/AlO_x/Nb junctions with the same or different Josephson critical current densities, J_c. The process also allows integration of high-J_c Superconductor-Ferromagnet-Superconductor (SFS) or SFS'S JJs on the first junction layer with Nb/Al/AlO_x/Nb trilayer junctions on the second junction layer, or vice versa. In the present node, the SFS trilayer, Nb/Ni/Nb is placed below the standard SIS trilayer and separated by one niobium wiring layer. The main purpose of integrating the SFS and SIS junction layers is to provide compact π-phase shifters in logic cells of superconductor digital circuits and random access memories, and thereby increase the integration scale and functional density of superconductor electronics. The current node of the two-junction-layer process has six planarized niobium layers, two layers of resistors, and 350-nm minimum feature size. The target Josephson critical current densities for the SIS junctions are 100 μA/μm^2 and 200 μA/μm^2. We present the salient features of the new process, fabrication details, and characterization results on two layers of Josephson junctions integrated into one process, both for the conventional and π-junctions.

cond-mat.supr-con↗

arXiv2017

Developments Toward a 250-nm, Fully Planarized Fabrication Process With Ten Superconducting Layers And Self-Shunted Josephson Junctions

We are developing a superconductor electronics fabrication process with up to nine planarized superconducting layers, stackable stud vias, self-shunted Nb/AlOx-Al/Nb Josephson junctions, and one layer of MoNx kinetic inductors. The minimum feature size of resistors and inductors in the process is 250 nm. We present data on the mutual inductance of Nb stripline and microstrip inductors with linewidth and spacing from 250 nm to 1 μm made on the same or adjacent Nb layers, as well as the data on the linewidth and resistance uniformity.

cond-mat.supr-con↗

arXiv2017

Properties of Unshunted and Resistively Shunted Nb/AlOx-Al/Nb Josephson Junctions With Critical Current Densities from 0.1 mA/μm^2 to 1 mA/μm^2

We investigated current-voltage characteristics of unshunted and externally shunted Josephson junctions (JJs) with high critical current densities, Jc, in order to extract their basic parameters and statistical characteristics for JJ modeling in superconducting integrated circuits and to assess their potential for future technology nodes. Nb/AlOx-Al/Nb JJs with diameters from 0.5 μm to 6 μm were fabricated using a fully planarized process with Mo or MoNx thin-film shunt resistors with sheet resistance Rsq = 2 Ω/sq and Rsq = 6 Ω/sq, respectively. We used our standard MIT LL process SFQ5ee to fabricate JJs with Jc = 0.1 mA/μm^2 and our new process SFQ5hs to make JJs with Jc = 0.2 mA/μm^2 and higher current densities up to about 1 mA/μm^2. Using LRC resonance features on the I-V characteristics of shunted JJs, we extract the inductance associated with molybdenum shunt resistors of 1.4 pH/sq. The main part this inductance, about 1.1 pH/sq, is the inductance of the 40-nm Mo resistor film, while the geometrical inductance of superconducting Nb wiring contributes the rest. We attribute this large inductance to kinetic inductance arising from the complex conductivity of a thin normal-metal film in an electromagnetic field with angular frequency ω, σ(ω)=σ0/(1+iωτ), where σ0 is the static conductivity and τ the electron scattering time. Using a resonance in a large-area unshunted high-Jc junction excited by a resistively coupled small-area shunted JJ, we extract the Josephson plasma frequency and specific capacitance of high-Jc junctions in 0.1 to 1 mA/μm^2 Jc range. We also present data on Jc targeting and JJ critical current spreads. We discuss using 0.2-mA/μm^2 JJs in VLSI Single Flux Quantum circuits and 0.5-mA/μm^2 JJs in high-density integrated circuits without shunt resistors.

cond-mat.supr-con↗