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Sebastian Buchwald

Publications and source records attributed to Sebastian Buchwald.

5 recordsLinked to original sources

Optimal Shuffle Code with Permutation Instructions

During compilation of a program, register allocation is the task of mapping program variables to machine registers. During register allocation, the compiler may introduce shuffle code, consisting of copy and swap operations, that transfers data between the registers. Three common sources of shuffle code are conflicting register mappings at joins in the control flow of the program, e.g, due to if-statements or loops; the calling convention for procedures, which often dictates that input arguments or results must be placed in certain registers; and machine instructions that only allow a subset of registers to occur as operands. Recently, Mohr et al. proposed to speed up shuffle code with special hardware instructions that arbitrarily permute the contents of up to five registers and gave a heuristic for computing such shuffle codes. In this paper, we give an efficient algorithm for generating optimal shuffle code in the setting of Mohr et al. An interesting special case occurs when no register has to be transferred to more than one destination, i.e., it suffices to permute the contents of the registers. This case is equivalent to factoring a permutation into a minimal product of permutations, each of which permutes up to five elements.

cs.DS

Solving the TTC 2011 Reengineering Case with GrGen.NET

The challenge of the Reengineering Case is to extract a state machine model out of the abstract syntax graph of a Java program. The extracted state machine offers a reduced view on the full program graph and thus helps to understand the program regarding the question of interest. We tackle this task employing the general purpose graph rewrite system GrGen.NET (www.grgen.net).

cs.PL

Compiler Optimization: A Case for the Transformation Tool Contest

An optimizing compiler consists of a front end parsing a textual programming language into an intermediate representation (IR), a middle end performing optimizations on the IR, and a back end lowering the IR to a target representation (TR) built of operations supported by the target hardware. In modern compiler construction graph-based IRs are employed. Optimization and lowering tasks can then be implemented with graph transformation rules. This case provides two compiler tasks to evaluate the participating tools regarding performance.

cs.PL

Solving the TTC 2011 Compiler Optimization Case with GrGen.NET

The challenge of the Compiler Optimization Case is to perform local optimizations and instruction selection on the graph-based intermediate representation of a compiler. The case is designed to compare participating tools regarding their performance. We tackle this task employing the general purpose graph rewrite system GrGen.NET (www.grgen.net).

cs.PL