arXiv subjects

Senol Gulgonul

Publications and source records attributed to Senol Gulgonul.

13 recordsLinked to original sources

arXiv2026

Weave: Verified Netlist-to-Schematic Conversion via Layered Graph Layout

Converting a SPICE netlist into a human-readable schematic is a longstanding problem in electronic design automation: simulators and machine-learning pipelines readily produce netlists, but designers reason about circuits through diagrams. Recent learning-based approaches translate netlists into schematics probabilistically, yet they provide no guarantee that the generated drawing preserves the original connectivity, and their accuracy degrades sharply as circuits grow. We present Weave, a deterministic converter that turns a SPICE netlist into an LTspice .asc schematic using a layered (Sugiyama-style) graph layout, and that certifies every output by a round-trip connectivity check: the generated schematic is re-parsed into a netlist and compared, net for net, against the input. A result is reported as correct only when the two partitions are identical, giving a binary correctness certificate rather than a similarity score. Weave runs entirely client-side as a single dependency-free file and embeds a pin table for 5093 LTspice symbols. On the identical public Circuits-LTSpice test set used by the state-of-the-art LLM converter Schemato (117 circuits, netlisted with LTspice itself), Weave achieves 100% compilation and 100% round-trip-verified connectivity equivalence, compared with Schemato's reported 76% compilation and a graph-edit-distance similarity of 0.35; notably, 73% of that set exceeds the five-component threshold beyond which Schemato reports losing connectivity accuracy. On a larger and harder corpus, the 3460 netlistable circuits of the official Analog Devices LTspice demo collection, Weave verifies exact connectivity for 88.4% of circuits, with the remaining failures concentrated in a single, well-characterized class of dense multi-pin power modules.

cs.AR↗

arXiv2026

From Stabilizing Regions to Certified Controllers: Closing the Selection Gap in Unified PID/PI Analysis for Time-Delay Plants

A recent unified treatment of PID tuning for time-delay plants (An, Tang, Sun, Zhang and Chen, Automatica, 2026) combines the D-partition method with a boundary gradient vector (BGV) to orient the boundaries of stabilizing, relative-stability and stability-margin regions. That method answers a feasibility question, namely where admissible gains lie, and it leaves a manual interior-point test to fix the unstable-pole count in each cell, with the choice of a single controller left to the user. This note makes three contributions. First, the one operation the BGV leaves manual, the absolute unstable-pole count, is available analytically: exactly for delay-free designs through a companion-matrix or Routh count, and through an argument-principle (Mikhailov) evaluation for retarded-type delay loops. Labelling every cell with its analytic count removes the interior-point test and decides the whole partition. Second, we add the step the BGV framework cannot reach, a time-domain selection rule that returns one certified controller: among monotone step responses we choose the minimum-settling-time PI gains, characterized by a tangency condition, with monotonicity guaranteed by external positivity (a nonnegative closed-loop impulse response). Third, we flag a neutral-type pitfall that the unified analysis never delimits: an ideal PID with derivative action on a first-order-plus-dead-time (FOPTD) plant is of neutral type, with a root chain on the imaginary axis when k Kd = T. We reproduce the authors' delay-free benchmark exactly, recovering both admissible Kp intervals, and demonstrate the full pipeline on a FOPTD plant, delivering a certified monotone, fast-settling PI controller that the region-only method can neither locate nor justify; the selected gains match an independent closed-form tangency rule to within one percent. All claims are validated numerically.

eess.SY↗

arXiv2026

Monotonic, Minimum-Settling-Time PI Tuning for First-Order-Plus-Dead-Time Plants: A Tangency Characterization

This paper studies PI tuning of a first-order-plus-dead-time (FOTD) plant for the fastest strictly monotone (zero-overshoot) setpoint step response, with monotonicity imposed on the plant output only. The minimizer is shown to be neither the pole-zero cancellation design nor the multiple real dominant pole (MRDP) design. It is a non-cancellation point at which the closed loop carries a slow real mode of small residue together with a faster underdamped complex pair, with the controller zero placed near the dominant real pole. The analytical centerpiece is a single tangency identity, tan(omega tau_star + alpha) = (a - b)/omega, which states that the monotonicity boundary is the locus where the secondary complex mode just fails to drive the output slope below zero. From this identity the design reduces to nested scalar conditions, realized at three levels of fidelity: an explicit closed-form rule, an exact response-based reduction, and a simulation-free transcendental system whose only non-elementary step is a fourth-order polynomial root. Relative to the critically damped Lambert-W cancellation rule the design reduces the 2% settling time by 14 to 52 percent and lowers the load integrated absolute error by 5 to 38 percent. We report the full cost: for delay-dominated plants (T/L <= 0.55) the control stays one-pulse, so the design is itself admissible in Huba's sense and merely faster, but for larger lag ratios the control becomes two-pulse, and across the range the maximum sensitivity rises from 1.39 to between 1.44 and 1.62. The contribution is positioned not as a uniformly better tuning but as the exact characterization of a specific, well-defined operating point, with an honest multi-metric comparison against established rules.

eess.SY↗

arXiv2026

Minimum settling-time PI control of pure delay processes under a hard non-overshoot constraint: exact boundary-contact characterization and the role of the MID point

We solve, exactly, the problem of minimum settling-time PI control of a pure delay process K e^{-Ls} under the hard time-domain constraint of zero overshoot, y(t) <= 1 for all t. The closed loop is a neutral delay system whose step response is piecewise polynomial on the delay segments, with geometrically decaying jump discontinuities at the segment boundaries t = kL. The constrained optimum is characterized by an equioscillation-type contact structure whose active contacts sit at echo boundaries: kink maxima grazing the setpoint, jumps landing on the settling-band edge, and boundary troughs anchored to it. The number of contact equations equals the number of gains, so the optimum is exactly computable for every band delta. In a closed-form regime, delta in [(3-2 sqrt2)/4, (3-2 sqrt2)/2] approx [4.29%, 8.58%], the optimal gains are independent of delta: K Kp = 1 - sqrt2/2, K Ki L = sqrt2/2, and the optimal settling time is Ts*(delta) = (4 - sqrt2 - 2 sqrt(delta)) L. Outside this window the optimum solves an explicit two-equation polynomial system per regime, and Ts*(delta) is a staircase with exact flats at integer multiples of L from jump-landing pinning. As delta -> 0 the optimal gains converge to K Kp = e^{-2}, K Ki L = 4 e^{-2}, the generic multiplicity-induced-dominancy (GMID) point of the neutral quasipolynomial. The GMID response satisfies the hard constraint and uniquely maximizes the decay rate; yet at every finite delta the delta-adapted optimum strictly beats the fixed GMID tuning, by about 40% at delta = 2%. The MID point is thus the limit of the optimal gains without ever being the optimal tuning. A numerical extension to first-order-plus-time-delay plants quantifies the speed/robustness trade across Ms in [1.39, 1.76].

eess.SY↗

arXiv2026

Closed-Form PI and PID Tuning of All-Pole Plants up to Third Order for Monotonic Minimum-Settling Step Responses

A unified, closed-form analytical PI/PID tuning method is presented for all-pole plants up to third order that yields a strictly monotonic (zero-overshoot) step response with minimum settling time. The design target is the binomial closed loop p^n/(s+p)^n, which is monotonic with robustness depending only on the order n. Because a fixed PI/PID cannot assign the closed-loop poles and the controller zeros independently, realizing this target exactly requires the controller zeros to be cancelled, which forces the controller numerator to divide the plant denominator. It follows that an exact, real-gained solution exists for any stable plant precisely up to second order with a PI controller and third order with a PID controller; beyond that the residual binomial factor acquires a complex pair of damping sqrt(3)/2, which a generic plant does not contain. Explicit gains are derived for first-order plants (PI), second-order plants with real and complex poles (PI and PID), and third-order plants with three real poles or one real pole plus a complex pair (PID). The freedom of the coincident designs is shown to be bounded: a quadratic nonnegativity condition gives the exact window of the design pole for strict monotonicity, which collapses at the pole-ratio-2 changeover for real poles and is nonempty for damping ratios above approximately 0.443 for complex poles. Monotonicity guarantees Mt = 1, hence Ms <= 2, phase margin >= 60 degrees, and gain margin >= 6 dB, tightening to universal constants for the binomial family. Load-disturbance attenuation obeys IAEd = 1/Ki, making the cost of cancellation explicit, and comparisons with SIMC, the CHR zero-overshoot rule, and deadbeat-fitted explicit formulas quantify the trade: at matched maximum sensitivity the proposed design settles faster than SIMC on the third-order example, with markedly lower controller gains and peak control effort.

eess.SY↗

arXiv2026

Analytical PI Tuning for Second-Order Plants with Monotonic Response and Minimum Settling Time

This study presents two analytical closed-form PI controller tuning solutions for second-order plants with real poles, each achieving monotonic step response and minimum settling time. The first solution employs pole-zero cancellation, placing the controller zero at the slower plant pole and reducing the closed-loop dynamics to a critically damped second-order system. The second solution, applicable when the plant pole ratio is less than two, places all three closed-loop poles at a common location without cancelling any plant pole, yielding a closed-loop transfer function with a triple real pole and a zero. Despite retaining a closed-loop zero, this solution achieves strictly faster settling time than the pole-zero cancellation method in its region of applicability. The two solutions coincide at the boundary pole ratio of two and together form a continuous piecewise-analytical tuning covering the full range of plant pole ratios. This study further establishes that closed-loop transfer functions of the form a^n/(s + a)^n possess a maximum sensitivity Ms together with phase margin and gain margin that are independent of the pole location a and depend solely on the order n, yielding universal robustness constants for each n. A closed-form expression GM(n) = 1 + sec^n(pi/n) is established for the gain margin of the family. Numerical verification confirms the analytical results across multiple plant configurations.

eess.SY↗

arXiv2026

HeceTokenizer: A Syllable-Based Tokenization Approach for Turkish Retrieval

HeceTokenizer is a syllable-based tokenizer for Turkish that exploits the deterministic six-pattern phonological structure of the language to construct a closed, out-of-vocabulary (OOV)-free vocabulary of approximately 8,000 unique syllable types. A BERT-tiny encoder (1.5M parameters) is trained from scratch on a subset of Turkish Wikipedia using a masked language modeling objective and evaluated on the TQuAD retrieval benchmark using Recall@5. Combined with a fine-grained chunk-based retrieval strategy, HeceTokenizer achieves 50.3% Recall@5, surpassing the 46.92% reported by a morphology-driven baseline that uses a 200 times larger model. These results suggest that the phonological regularity of Turkish syllables provides a strong and resource-light inductive bias for retrieval tasks.

cs.CL↗

arXiv2025

Revisiting Chien-Hrones-Reswick Method for an Analytical Solution

This study presents an analytical method for tuning PI controllers in First-Order with Time Delay (FOTD) systems, leveraging the Lambert W function. The Lambert W function enables exact pole placement, yielding analytical expressions for PI gains. The proposed approach identifies a critical condition that achieves a step response without overshoot with minimum settling time, while also providing explicit tuning rules for systems where controlled overshoot is specified. The method demonstrates strong agreement with established empirical Chien-Hrones-Reswick tuning rules for both non-overshooting and overshooting cases, bridging the gap between theoretical analysis and empirical results.

eess.SY↗

arXiv2025

PID Tuning via Desired Step Response Curve Fitting

This paper presents a PID tuning method based on step response curve fitting (PID-SRCF) that utilizes L2-norm minimization for precise reference tracking and explicit transient response shaping. The algorithm optimizes controller parameters by minimizing the root-mean-square error between desired and actual step responses. The proposed approach determines optimal PID parameters by matching any closed-loop response to a desired system step response. Practically a first-order plus time delay model or a second-order system with defined settling time and overshoot requirements are preferred. The method has open-source implementation using constrained nonlinear optimization in MATLAB. Comparative evaluations demonstrate that PID-SRCF can replace known analytical methods like Ziegler Nichols, Lambda Tuning, Pole Placement, Dominant Pole and MATLAB proprietary PID tuning applications.

eess.SY↗

arXiv2025

Development and Testing of a Low Cost Ultrasonic Leak Detector

This study focuses on the development of an ultrasonic leak detection system utilizing the Arduino Nano 33 BLE Sense Rev2 board. The research aimed to create a compact and cost-effective solution for identifying leaks in high-pressure pipes. Algorithms were designed to enable lossless recording and processing of sound data captured by the onboard MEMS microphone. Key signal processing techniques, including the implementation of an IIR high-pass filter and RMS calculation, were employed to detect ultrasonic frequencies associated with leaks. The system was tested on a pressurized pipe setup, demonstrating its ability to accurately identify leaks. The results highlight the system's effectiveness, with its compact design and low cost making it suitable for a wide range of industrial applications. This research contributes a practical and accessible tool for leak detection, offering potential benefits in industrial applications.

eess.SP↗

arXiv2025

IAE Optimized PID Tuning with Phase Margin and Crossover Frequency Constraints

This paper presents PMwc-Tune, a novel PID tuning method that uniquely combines frequency-domain robustness constraints with time-domain performance optimization through constrained nonlinear programming. The key contribution is a unified formulation that simultaneously enforces phase margin and crossover frequency requirements (via nonlinear equality constraints) while minimizing the Integral Absolute Error (IAE) of the closed-loop response. The algorithm employs Sequential Quadratic Programming (SQP) to solve this constrained optimization problem, guaranteeing specification attainment within numerical tolerances while optimizing transient performance. Numerical validation on benchmark systems demonstrates precise convergence to design targets (phase margin and crossover frequency errors <1%) with a 4.6% IAE reduction compared to MATLAB's pidtune. The open-source implementation provides both methodological transparency and practical design flexibility, enabling PID controllers that rigorously balance frequency-domain robustness and time-domain performance.

eess.SY↗

arXiv2025

IAE Optimized PID Tuning via Second Order Step Response Target Matching

This paper presents SOSTIAE (Second-Order System Target IAE), a novel PID tuning method that combines IAE minimization with explicit transient response shaping for practical control applications. The algorithm generates optimal PID parameters by matching the closed-loop response to a target second-order system with user-defined settling time (Ts) and percent overshoot (PO), while maintaining the conventional IAE performance metric. Comparative evaluations on first to third-order systems demonstrate that SOSTIAE consistently outperforms MATLAB's proprietary pidtune function, achieving 47-67% lower overshoot and up to 26% better IAE performance for higher-order plants. The constrained optimization framework ensures physically realizable controllers by enforcing non-negative PID gains and stability criteria, addressing known limitations of unconstrained IAE methods. Results indicate that SOSTIAE provides engineers with a systematic alternative for PID tuning when transient specifications and practical implementation constraints are critical.

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arXiv2025

Sparking Curiosity in Digital System Design Lectures with Take Home Labs

Digital system design lectures are mandatory in the electrical and electronics engineering curriculum. Besides HDL simulators and viewers, FPGA boards are necessary for the real implementation of HDL, which were previously costly for students. With the emergence of low-cost FPGA boards, the use of take-home labs is increasing. The COVID-19 pandemic has further accelerated this process. Traditional lab sessions have limitations, prompting the exploration of take-home lab kits to enhance learning flexibility and engagement. This study aims to evaluate the effectiveness of a low-cost take-home lab kit, consisting of a Tang Nano 9K FPGA board and a Saleae Logic Analyzer, in improving students' practical skills and sparking curiosity in digital system design. The research was conducted in the EEE 303 Digital Design lecture. Students used the Tang Nano 9K FPGA and Saleae Logic Analyzer for a term project involving PWM signal generation. Data was collected through a survey assessing the kit's impact on learning and engagement. Positive Acceptance: 75% of students agreed or strongly agreed that the take-home lab kit was beneficial. Preference for Lab Types: 60% of students preferred classical weekly lab hours over take-home labs. Increased Curiosity: 65% of students conducted additional, unassigned experiments, indicating heightened interest and engagement. The take-home lab kit effectively aids in learning practical aspects of digital system design and stimulates curiosity, though some students prefer traditional lab sessions for group work.

cs.CY↗