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Shaolan Li

Publications and source records attributed to Shaolan Li.

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A Reconfigurable Pipelined-SAR ADC with Embedded Compression for Temporal Compressed-Sensing Ultrasound Imaging

Compact ultrasound imaging systems are increasingly constrained by receiver-side sampling, conversion, memory, and data-transfer requirements. This work presents a compressed-sensing pipelined successive-approximation-register analog-to-digital converter (CS-SAR ADC) for acquisition-side temporal compression of pre-beamformed medical ultrasound radio-frequency (RF) data. Pseudo-random polarity modulation and charge-domain accumulation are embedded in the SAR sampling network so that multiple consecutive RF samples are encoded into one measurement before quantization, supporting temporal compression ratios of $N_{cT}=1$, 2, and 4. The compressed outputs are recovered off chip using a probe-specific pulse-dictionary RF model and then processed with conventional ultrasound beamforming. A 65-nm CMOS prototype was measured with a 1.2-V supply and 50-MHz master clock. In the non-compressed mode, it operates at 10 MS/s, consumes 964.49~$\mu$W, and achieves 44.12-dB SNDR and 56.40-dB SFDR for a 7.7-kHz input. The ADC output rates decrease to 5 MS/s and 2.5 MS/s for $N_{cT}=2$ and 4. Across all evaluated RF traces, median NCC values were 0.981 and 0.932, with median NRMSE values of 0.36 and 0.56, respectively. Wire-phantom localization error remained below 0.04 mm with no appreciable FWHM degradation. In the speckle-rich cyst phantom, SSIM remained 0.94 and 0.87, while CNR decreased from 3.534 in the reference to 2.047 and 1.379. These results demonstrate a hardware-realistic tradeoff in which temporal compression substantially reduces ADC conversion count and output data rate while preserving point-target geometry, whereas low-contrast cyst conspicuity is more compression-sensitive.

physics.med-ph

A Global-Local Optimization Approach for Asynchronous SAR ADC Design

This paper presents a system-level optimization framework for automated asynchronous SAR ADC design, addressing the limitations of block-level methods in terms of suboptimal performance and manual effort. The proposed approach integrates a fast global optimizer with a multi-fidelity local optimizer to efficiently handle high-dimensionality and expensive simulation cost. Experimental results from 12 design cases, covering 7- and 12-bit resolutions and a frequency range of 100 kHz to 250 MHz, demonstrate highly competitive performance compared with prior works.

math.OC