arXiv subjects

Shibarchi Majumder

Publications and source records attributed to Shibarchi Majumder.

3 recordsLinked to original sources

arXiv2022

PaRTAA: A Real-time Multiprocessor for Mixed-Criticality Airborne Systems

Mixed-criticality systems, where multiple systems with varying criticality-levels share a single hardware platform, require isolation between tasks with different criticality-levels. Isolation can be achieved with software-based solutions or can be enforced by a hardware level partitioning. An asymmetric multiprocessor architecture offers hardware-based isolation at the cost of underutilized hardware resources, and the inter-core communication mechanism is often a single point of failure in such architectures. In contrast, a partitioned uniprocessor offers efficient resource utilization at the cost of limited scalability. We propose a partitioned real-time asymmetric architecture (PaRTAA) specifically designed for mixed-criticality airborne systems, featuring robust partitioning within processing elements for establishing isolation between tasks with varying criticality. The granularity in the processing element offers efficient resource utilization where inter-dependent tasks share the same processing element for sequential execution while preserving isolation, and independent tasks simultaneously execute on different processing elements as per system requirements.

cs.AR↗

arXiv2022

Ærø: A Platform Architecture for Mixed-Criticality Airborne Systems

Real-time embedded platforms with resource constraints can take the benefits of mixed-criticality system where applications with different criticality-level share computational resources, with isolation in the temporal and spatial domain. A conventional software-based isolation mechanism adds additional overhead and requires certification with the highest level of criticality present in the system, which is often an expensive process. In this article, we present a different approach where the required isolation is established at the hardware-level by featuring partitions within the processor. A four-stage pipelined soft-processor with replicated resources in the data-path is introduced to establish isolation and avert interference between the partitions. A cycle-accurate scheduling mechanism is implemented in the hardware for hard-real-time partition scheduling that can accommodate different periodicity and execution time for each partition as per user needs, while preserving time-predictability at the individual application level. Applications running within a partition has no sense of the virtualization and can execute either on a host-software or directly on the hardware. The proposed architecture is implemented on FPGA thread and demonstrated with an avionics use case.

eess.SY↗

arXiv2020

Markovian Performance Model for Token Bucket Filter with Fixed and Varying Packet Sizes

We consider a token bucket mechanism serving a heterogeneous flow with a focus on backlog, delay and packet loss properties. Previous models have considered the case for fixed size packets, i.e. "one token per packet" with and M/D/1 view on queuing behavior. We partition the heterogeneous flow into several packet size classes with individual Poisson arrival intensities. The accompanying queuing model is a "full state" model, i.e. buffer content is not reduced to a single quantity but encompasses the detailed content in terms of packet size classes. This yields a high model cardinality for which upper bounds are provided. Analytical results include class specific backlog, delay and loss statistics and are accompanied by results from discrete event simulation.

cs.NI↗