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Shibnath Mandal

Publications and source records attributed to Shibnath Mandal.

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Electronic access to glass transition in supercooled ionic liquids using ambipolar transistor

Relaxation dynamics of supercooled liquids approaching glassy arrest remain a central challenge in integrated electronic architectures, where conventional rheometry becomes incompatible. Here, we demonstrate that an ambipolar PdSe$_2$ field-effect transistor functions as an electrical probe capable of resolving ion-specific relaxation dynamics in fragile ionic glass formers and semiquantitatively inferring rheological parameters within an operating device environment. Temperature evolution of the transfer curve hysteresis and time-resolved current transients under ionic-gate pulse reveal a non-Arrhenius fragile slowdown. We track the continuous reduction of dynamically equilibrated liquid regions approaching the glass transition through an electrically accessible quantity $p_\text{eq}(T)$, quantifying the fraction of the mobile ions able to relax within the experimental timescale. Upon cooling, $p_\text{eq}$ collapses sharply as mobile regions fragment into percolating fractal clusters, consistent with a reduction of configurational entropy predicted for fragile glass formers. This approach enables temperature-dependent scaling of viscosity and extraction of characteristic temperatures marking the ergodic-to-nonergodic crossover, within a solid-state device architecture where conventional rheological characterization is inapplicable. Further, polymer confinement of the ionic liquid shifts these characteristic temperatures upward, demonstrating the sensitivity of this method to structural constraints imposed by the polymer matrix.

cond-mat.soft

Tailored 1D/2D Van der Waals Heterostructures for Unified Analog and Digital Electronics

We report a sequential two-step vapor deposition process for growing mixed-dimensional van der Waals (vdW) materials, specifically Te nanowires (1D) and MoS$_2$ (2D), on a single SiO$_2$ wafer. Our growth technique offers a unique potential pathway to create large scale, high-quality, defect-free interfaces. The assembly of samples serves a twofold application: first, the as-prepared heterostructures (Te NW/MoS$_2$) provide insights into the atomically thin depletion region of a 1D/2D vdW diode, as revealed by electrical transport measurements and density functional theory-based quantum transport calculations. The charge transfer at the heterointerface is confirmed using Raman spectroscopy and Kelvin probe force microscopy (KPFM). We also observe modulation of the rectification ratio with varying applied gate voltage. Second, the non-hybrid regions on the substrate, consisting of the as-grown individual Te nanowires and MoS$_2$ microstructures, are utilized to fabricate separate p- and n-FETs, respectively. Furthermore, the ionic liquid gating helps to realize low-power CMOS inverter and all basic logic gate operations using a pair of n- and p- field-effect transistors (FETs) on Si/SiO$_2$ platform. This approach also demonstrates the potential for unifying diode and CMOS circuits on a single platform, opening opportunities for integrated analog and digital electronics.

cond-mat.mes-hall