arXiv subjects

Shifan Xu

Publications and source records attributed to Shifan Xu.

10 recordsLinked to original sources

arXiv2026

OQRAM: Oblivious Quantum Random Access Memory for Securing Delegated Quantum Queries

Quantum query is a basic subroutine in many quantum algorithms, and Quantum Random Access Memory (QRAM) provides a natural way to realize such coherent query access. In delegated settings, however, a standard QRAM query interface can expose sensitive information to the server. This paper introduces oblivious QRAM, a cryptographic abstraction for privacy-preserving delegated coherent query access. The protocol consists of an offline refresh phase and an online protected query phase. The database is stored in an encrypted and shuffled layout, and each query is protected by coherent address masking using either a quantum-secure pseudorandom permutation (qPRP) based method or a quantum one-time pad (qOTP) based method. In the adopted client model, the online protection adds only modest quantum overhead beyond the query register, avoiding the exponential quantum resources that would otherwise be required by an equivalent local QRAM construction. The qPRP-based variant also supports multi-query use by distributing database refresh across multiple queries to reduce classical communication. To address malicious servers, decoy checks are further incorporated to strengthen privacy protection and enable probabilistic tampering detection. Compared with fully blind quantum computing, this framework provides a lighter abstraction tailored to private delegated QRAM access, significantly reducing quantum resource requirements on both the client and server sides and achieving an exponential reduction in quantum communication.

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arXiv2026

Asymptotically Optimal Depth Fermionic Permutation on 2D Grid Quantum Architecture without Ancillas

Simulating fermionic systems on qubit hardware involves many nonlocal interactions, and efficient routing of these interactions is critical to the overall cost of fermionic simulation algorithms. Recent works reduce this routing overhead to polylogarithmic depth under all-to-all connectivity, but degrade to $O(\sqrt{N}\log N)$ for $N$ fermionic modes on 2D nearest-neighbor architectures. We present a fermionic permutation protocol tailored to 2D grid architectures that achieves the optimal $O(\sqrt{N})$ depth with $O(N\sqrt{N})$ nearest-neighbor gates and no ancilla qubits, measurements, or classical feedforward. For $N=L^2$ modes, the CNOT depth is at most $10L+12$. This matches the $\Omega(\sqrt{N})$ lower bound, which holds even when $O(N)$ ancillas and classical feedforward are permitted. We further construct an $O(\sqrt{N})$-depth transformation between the Jordan--Wigner, Bravyi--Kitaev, and Parity encodings on the 2D grid via a Hilbert-curve layout, extending our result to all three encodings. Benchmarks on a standalone fermionic permutation circuit, the fermionic fast Fourier transform, and Trotter simulation of a sparse SYK model demonstrate that the practical crossover is near the analytical depth-bound breakeven at $L=6$ ($N=36$), followed by consistent reductions in circuit depth and spacetime volume and higher estimated no-fault probability in the early fault-tolerant regime, growing with system size.

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arXiv2026

Efficient Routing of Quantum LDPC Codes on Programmable 2D Toric Architectures

Quantum low-density parity-check codes are promising candidates towards scalable fault-tolerant quantum computation. Among these, bivariate bicycle (BB) codes offer superior encoding rates and large code distance compared to surface codes. However, their requirement on long-range stabilizer measurements poses significant challenges for implementation on realistic hardware with limited connectivity, such as superconducting circuit platforms. In this work, we introduce a novel hardware-software co-design that leverages a programmable communication network architecture to address these limitations. Our approach utilizes a 2D toric network of oscillators as a flexible communication fabric linking qubits at each site. Such architecture significantly reduces the number of long-range couplers required from $O(n)$ to $O(\sqrt{n})$. Dual-rail qubits, along with native gates including Swap-Wait-Swap gates and beamsplitter SWAPs, ensure that long-range two-qubit gates can be executed with high fidelity and low latency. To further enhance performance, our qubit layout and routing algorithm utilize symmetries of the codes and enable maximum parallelism for long-range two-qubit gates, maintaining a low syndrome extraction cycle duration and scalability over the code length. We perform circuit-level simulation with realistic noise modeling based on experimental hardware parameters, observing an logical error rate per logical qubit per cycle of 3.06\% for $[[18, 4, 4]]$ BB code, 2.6$\times$ less than the existing experimental result. These findings provide a practical roadmap and identify key technological advancements needed to achieve low-overhead fault-tolerant quantum computing at scale.

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arXiv2026

In-Situ Simultaneous Magic State Injection on Arbitrary CSS qLDPC Codes

Quantum low-density parity-check (qLDPC) codes can encode many logical qubits within a single code block at low physical qubit overhead, yet magic state injection into such codes remains largely underexplored. Existing state injection proposals for qLDPC codes predominantly follow an external prepare-and-transfer paradigm, in which raw magic states are prepared outside the target code block and subsequently injected via inter-code operations. We propose the first \emph{in-situ} magic state injection: a scheme in which logical magic states are directly prepared within a qLDPC memory block, only using resources required for syndrome extraction. We show that our scheme is generalizable to any CSS qLDPC code, with examples of circuit-level simulations on the $[[144,12,12]]$ Bivariate Bicycle (BB) code and the $[[225,9,4]]$ Hypergraph Product code. We focus on a regime where correlated injection errors are negligible. In the BB code, this corresponds to a configuration that simultaneously injects four logical $|Y\rangle$ states. Under a uniform depolarizing noise model with physical error rate $10^{-3}$, this achieves an injection error rate of $1.62 \times 10^{-3}$ per logical qubit, while the correlated-error contribution is only $2 \times 10^{-5}$ per logical qubit (about $1\%$ of the injection error rate). Under a hardware-motivated asymmetric noise model where single-qubit gate errors are $10\%$ of two-qubit gate errors, the injection error rate per logical qubit falls to $ 6.7 \times 10^{-4} $, below the error rate ($ 10^{-3} $) of the two-qubit gates used to encode the magic states. Its simplicity allows our scheme to be applied to arbitrary CSS qLDPC codes using only the ancilla qubits native to syndrome extraction, and yield a reduction in space overhead relative to both prepare-and-transfer approaches and surface-code-based magic state injection schemes.

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arXiv2026

Distilling Magic States in the Bicycle Architecture

Magic State Distillation is considered to be one of the promising methods for supplying the non-Clifford resources required to achieve universal fault tolerance. Conventional MSD protocols implemented in surface codes often require multiple code blocks and lattice surgery rounds, resulting in substantial qubit overhead, especially at low target error rates. In this work, we present practical magic state distillation factories on Bivariate Bicycle (BB) codes that execute Pauli-measurement-based Clifford circuits inside a single BB code block. We formulate distillation circuit design as a joint optimization of logical qubit mapping, gate scheduling, measurement nativization, and protocol compression via qubit recycling. Based on detailed resource analysis and simulations, our BB factories have space-time volume comparable to that of leading distillation factories while delivering lower target error at a smaller qubit footprint, and are particularly compelling as second-round distillers following magic state cultivations.

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arXiv2026

FTCircuitBench: A Benchmark Suite for Fault-Tolerant Quantum Compilation and Architecture

Realizing large-scale quantum advantage is expected to require quantum error correction (QEC), making the compilation and optimization of logical operations a critical area of research. Logical computation imposes distinct constraints and operational paradigms that differ from those of the Noisy Intermediate-Scale Quantum (NISQ) regime, motivating the continued evolution of compilation tools. Given the complexity of this emerging stack, where factors such as gate decomposition precision and computational models must be co-designed, standardized benchmarks and toolkits are valuable for evaluating progress. To support this need, we introduce FTCircuitBench, which serves as: (1) a benchmark suite of impactful quantum algorithms, featuring pre-compiled instances in both Clifford+T and Pauli Based Computation models; (2) a modular end-to-end pipeline allowing users to compile and decompose algorithms for various fault-tolerant architectures, supporting both prebuilt and custom optimization passes; and (3) a toolkit for evaluating the impact of algorithms and optimization across the full compilation stack, providing detailed numerical analysis at each stage. FTCircuitBench is fully open-sourced and maintained on Github.

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arXiv2025

Fat-Tree QRAM: A High-Bandwidth Shared Quantum Random Access Memory for Parallel Queries

Quantum Random Access Memory (QRAM) is a crucial architectural component for querying classical or quantum data in superposition, enabling algorithms with wide-ranging applications in quantum arithmetic, quantum chemistry, machine learning, and quantum cryptography. In this work, we introduce Fat-Tree QRAM, a novel query architecture capable of pipelining multiple quantum queries simultaneously while maintaining desirable scalings in query speed and fidelity. Specifically, Fat-Tree QRAM performs $O(\log (N))$ independent queries in $O(\log (N))$ time using $O(N)$ qubits, offering immense parallelism benefits over traditional QRAM architectures. To demonstrate its experimental feasibility, we propose modular and on-chip implementations of Fat-Tree QRAM based on superconducting circuits and analyze their performance and fidelity under realistic parameters. Furthermore, a query scheduling protocol is presented to maximize hardware utilization and access the underlying data at an optimal rate. These results suggest that Fat-Tree QRAM is an attractive architecture in a shared memory system for practical quantum computing.

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arXiv2024

Faulty towers: recovering a functioning quantum random access memory in the presence of defective routers

Proposals for quantum random access memory (QRAM) generally have a binary-tree structure, and thus require hardware that is exponential in the depth of the QRAM. For solid-state based devices, a fabrication yield that is less than $100\%$ implies that certain addresses at the bottom of the tree become inaccessible if a router in the unique path to that address is faulty. We discuss how to recover a functioning QRAM in the presence of faulty routers. We present the \texttt{IterativeRepair} algorithm, which constructs QRAMs layer by layer until the desired depth is reached. This algorithm utilizes ancilla flag qubits which reroute queries to faulty routers. We present a classical algorithm \texttt{FlagQubitMinimization} that attempts to minimize the required number of such ancilla. For a router failure rate of $1\%$ and a QRAM of depth $n=13$, we expect that on average 430 addresses need repair: we require only 1.5 ancilla flag qubits on average to perform this rerouting.

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arXiv2024

Architectures for Heterogeneous Quantum Error Correction Codes

Quantum Error Correction (QEC) is essential for future quantum computers due to its ability to exponentially suppress physical errors. The surface code is a leading error-correcting code candidate because of its local topological structure, experimentally achievable thresholds, and support for universal gate operations with magic states. However, its physical overhead scales quadratically with number of correctable errors. Conversely, quantum low-density parity-check (qLDPC) codes offer superior scaling but lack, on their own, a clear path to universal logical computation. Therefore, it is becoming increasingly evident is becoming that there are significant advantages to designing architectures using multiple codes. Heterogeneous architectures provide a clear path to universal logical computation as well as the ability to access different resource trade offs. To address this, we propose integrating the surface code and gross code using an ancilla bus for inter-code data movement. This approach involves managing trade-offs, including qubit overhead, a constrained instruction set, and gross code (memory) routing and management. While our focus is on the gross-surface code architecture, our method is adaptable to any code combination and the constraints generated by that specific architecture. Motivated by the potential reduction of physical qubit overhead, an ever important feature in the realization of fault tolerant computation, we perform the first full system study of heterogeneous error-correcting codes, discovering architectural trade-offs and optimizing around them. We demonstrate physical qubit reductions of up to 6.42x when executing an algorithm to a specific logical error rate, at the cost of up to a 3.43x increase in execution time.

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arXiv2023

Systems Architecture for Quantum Random Access Memory

Operating on the principles of quantum mechanics, quantum algorithms hold the promise for solving problems that are beyond the reach of the best-available classical algorithms. An integral part of realizing such speedup is the implementation of quantum queries, which read data into forms that quantum computers can process. Quantum random access memory (QRAM) is a promising architecture for realizing quantum queries. However, implementing QRAM in practice poses significant challenges, including query latency, memory capacity and fault-tolerance. In this paper, we propose the first end-to-end system architecture for QRAM. First, we introduce a novel QRAM that hybridizes two existing implementations and achieves asymptotically superior scaling in space (qubit number) and time (circuit depth). Like in classical virtual memory, our construction enables queries to a virtual address space larger than what is actually available in hardware. Second, we present a compilation framework to synthesize, map, and schedule QRAM circuits on realistic hardware. For the first time, we demonstrate how to embed large-scale QRAM on a 2D Euclidean space, such as a grid layout, with minimal routing overhead. Third, we show how to leverage the intrinsic biased-noise resilience of the proposed QRAM for implementation on either Noisy Intermediate-Scale Quantum (NISQ) or Fault-Tolerant Quantum Computing (FTQC) hardware. Finally, we validate these results numerically via both classical simulation and quantum hardware experimentation. Our novel Feynman-path-based simulator allows for efficient simulation of noisy QRAM circuits at a larger scale than previously possible. Collectively, our results outline the set of software and hardware controls needed to implement practical QRAM.

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