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Simon J. Devitt

Publications and source records attributed to Simon J. Devitt.

At least 37 records · Page 2Linked to original sources
arXiv2019

Time versus Hardware: Reducing Qubit Counts with a (Surface Code) Data Bus

We introduce a data bus, for reducing the qubit counts within quantum computations (protected by surface codes). For general computations, an automated trade-off analysis (software tool and source code are open sourced and available online) is performed to determine to what degree qubit counts are reduced by the data bus: is the time penalty worth the qubit count reductions? We provide two examples where the qubit counts are convincingly reduced: 1) interaction of two surface code patches on NISQ machines with 28 and 68 qubits, and 2) very large-scale circuits with a structure similar to state-of-the-art quantum chemistry circuits. The data bus has the potential to transform all layers of the quantum computing stack (e.g., as envisioned by Google, IBM, Riggeti, Intel), because it simplifies quantum computation layouts, hardware architectures and introduces lower qubits counts at the expense of a reasonable time penalty.

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arXiv2019

Really Small Shoe Boxes - On Realistic Quantum Resource Estimation

Reliable resource estimation and benchmarking of quantum algorithms is a critical component of the development cycle of viable quantum applications for quantum computers of all sizes. Determining critical resource bottlenecks in algorithms, especially when resource intensive error correction protocols are required, will be crucial to reduce the cost of implementing viable algorithms on actual quantum hardware.

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arXiv2018

A Specification Format and a Verification Method of Fault-Tolerant Quantum Circuits

Quantum computations are expressed in general as quantum circuits, which are specified by ordered lists of quantum gates. The resulting specifications are used during the optimisation and execution of the expressed computations. However, the specification format makes it difficult to verify that optimised or executed computations still conform to the initial gate list specifications: showing the computational equivalence between two quantum circuits expressed by different lists of quantum gates is exponentially complex in the worst case. In order to solve this issue, this work presents a derivation of the specification format tailored specifically for fault-tolerant quantum circuits. The circuits are considered a form consisting entirely of single qubit initialisations, CNOT gates and single qubit measurements (ICM form). This format allows, under certain assumptions, to efficiently verify optimised (or implemented) computations. Two verification methods based on checking stabiliser circuit structures are presented.

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arXiv2018

A local and scalable lattice renormalization method for ballistic quantum computation

A recent proposal has shown that it is possible to perform linear-optics quantum computation using a ballistic generation of the lattice. Yet, due to the probabilistic generation of its cluster state, it is not possible to use the fault-tolerant Raussendorf lattice, which requires a lower failure rate during the entanglement-generation process. Previous work in this area showed proof-of-principle linear-optics quantum computation, while this paper presents an approach to it which is more practical, satisfying several key constraints. We develop a classical measurement scheme, that purifies a large faulty lattice to a smaller lattice with entanglement faults below threshold. A single application of this method can reduce the entanglement error rate to $7\%$ for an input failure rate of $25\%$. Thus, we can show that it is possible to achieve fault tolerance for ballistic methods.

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arXiv2018

Lattice Surgery on the Raussendorf Lattice

Lattice surgery is a method to perform quantum computation fault-tolerantly by using operations on boundary qubits between different patches of the planar code. This technique allows for universal planar-code computation without eliminating the intrinsic two-dimensional nearest-neighbor properties of the surface code that eases physical hardware implementations. Lattice-surgery approaches to algorithmic compilation and optimization have been demonstrated to be more resource efficient for resource-intensive components of a fault-tolerant algorithm, and consequently may be preferable over braid-based logic. Lattice surgery can be extended to the Raussendorf lattice, providing a measurement-based approach to the surface code. In this paper we describe how lattice surgery can be performed on the Raussendorf lattice and therefore give a viable alternative to computation using braiding in measurement based implementations of topological codes.

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arXiv2018

Holonomic Surface Codes for Fault-Tolerant Quantum Computation

Surface codes can protect quantum information stored in qubits from local errors as long as the per-operation error rate is below a certain threshold. Here we propose holonomic surface codes by harnessing the quantum holonomy of the system. In our scheme, the holonomic gates are built via auxiliary qubits rather than the auxiliary levels in multilevel systems used in conventional holonomic quantum computation. The key advantage of our approach is that the auxiliary qubits are in their ground state before and after each gate operation, so they are not involved in the operation cycles of surface codes. This provides an advantageous way to implement surface codes for fault-tolerant quantum computation.

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arXiv2018

Surface Code Error Correction on a Defective Lattice

The yield of physical qubits fabricated in the laboratory is much lower than that of classical transistors in production semiconductor fabrication. Actual implementations of quantum computers will be susceptible to loss in the form of physically faulty qubits. Though these physical faults must negatively affect the computation, we can deal with them by adapting error correction schemes. In this paper We have simulated statically placed single-fault lattices and lattices with randomly placed faults at functional qubit yields of 80%, 90% and 95%, showing practical performance of a defective surface code by employing actual circuit constructions and realistic errors on every gate, including identity gates. We extend Stace et al.'s superplaquettes solution against dynamic losses for the surface code to handle static losses such as physically faulty qubits. The single-fault analysis shows that a static loss at the periphery of the lattice has less negative effect than a static loss at the center. The randomly-faulty analysis shows that 95% yield is good enough to build a large scale quantum computer. The local gate error rate threshold is $\sim 0.3\%$, and a code distance of seven suppresses the residual error rate below the original error rate at $p=0.1\%$. 90% yield is also good enough when we discard badly fabricated quantum computation chips, while 80% yield does not show enough error suppression even when discarding 90% of the chips. We evaluated several metrics for predicting chip performance, and found that the average of the product of the number of data qubits and the cycle time of a stabilizer measurement of stabilizers gave the strongest correlation with post-correction residual error rates. Our analysis will help with selecting usable quantum computation chips from among the pool of all fabricated chips.

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arXiv2017

Optimization of Lattice Surgery is NP-Hard

The traditional method for computation in either the surface code or in the Raussendorf model is the creation of holes or "defects" within the encoded lattice of qubits that are manipulated via topological braiding to enact logic gates. However, this is not the only way to achieve universal, fault-tolerant computation. In this work, we focus on the Lattice Surgery representation, which realizes transversal logic operations without destroying the intrinsic 2D nearest-neighbor properties of the braid-based surface code and achieves universality without defects and braid based logic. For both techniques there are open questions regarding the compilation and resource optimization of quantum circuits. Optimization in braid-based logic is proving to be difficult and the classical complexity associated with this problem has yet to be determined. In the context of lattice-surgery-based logic, we can introduce an optimality condition, which corresponds to a circuit with the lowest resource requirements in terms of physical qubits and computational time, and prove that the complexity of optimizing a quantum circuit in the lattice surgery model is NP-hard.

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arXiv2017

Fault-Tolerant High Level Quantum Circuits: Form, Compilation and Description

Fault-tolerant quantum error correction is a necessity for any quantum architecture destined to tackle interesting, large-scale problems. Its theoretical formalism has been well founded for nearly two decades. However, we still do not have an appropriate compiler to produce a fault-tolerant, error corrected description from a higher level quantum circuit for state of the art hardware models. There are many technical hurdles, including dynamic circuit constructions that occur when constructing fault-tolerant circuits with commonly used error correcting codes. We introduce a package that converts high level quantum circuits consisting of commonly used gates into a form employing all decompositions and ancillary protocols needed for fault-tolerant error correction. We call this form the (I)initialisation, (C)NOT, (M)measurement form (ICM) and consists of an initialisation layer of qubits into one of four distinct states, a massive, deterministic array of CNOT operations and a series of time ordered $X$- or $Z$-basis measurements. The form allows a more flexbile approach towards circuit optimisation. At the same time, the package outputs a standard circuit or a canonical geometric description which is a necessity for operating current state-of-the-art hardware architectures using topological quantum codes.

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arXiv2017

Lattice Surgery Translation for Quantum Computation

In this paper we outline a method for a compiler to translate any non fault tolerant quantum circuit to the geometric representation of the lattice surgery error-correcting code using inherent merge and split operations. Since the efficiency of state distillation procedures has not yet been investigated in the lattice surgery model, their translation is given as an example using the proposed method. The resource requirements seem comparable to the defect-based state distillation process, but modularity and eventual implementability allow the lattice surgery model to be an interesting alternative to braiding.

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arXiv2016

High-speed quantum networking by ship

Networked entanglement is an essential component for a plethora of quantum computation and communication protocols. Direct transmission of quantum signals over long distances is prevented by fibre attenuation and the no-cloning theorem, motivating the development of quantum repeaters, designed to purify entanglement, extending its range. Quantum repeaters have been demonstrated over short distances, but error-corrected, global repeater networks with high bandwidth require new technology. Here we show that error corrected quantum memories installed in cargo containers and carried by ship can provide a flexible connection between local networks, enabling low-latency, high-fidelity quantum communication across global distances at higher bandwidths than previously proposed. With demonstrations of technology with sufficient fidelity to enable topological error-correction, implementation of the quantum memories is within reach, and bandwidth increases with improvements in fabrication. Our approach to quantum networking avoids technological restrictions of repeater deployment, providing an alternate path to a worldwide Quantum Internet.

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arXiv2016

Wire Recycling for Quantum Circuit Optimization

Quantum information processing is expressed using quantum bits (qubits) and quantum gates which are arranged in the terms of quantum circuits. Here, each qubit is associated to a quantum circuit wire which is used to conduct the desired operations. Most of the existing quantum circuits allocate a single quantum circuit wire for each qubit and, hence, introduce a significant overhead. In fact, qubits are usually not needed during the entire computation but only between their initialization and measurement. Before and after that, corresponding wires may be used by other qubits. In this work, we propose a solution which exploits this fact in order to optimize the design of quantum circuits with respect to the required wires. To this end, we introduce a representation of the lifetimes of all qubits which is used to analyze the respective need for wires. Based on this analysis, a method is proposed which "recycles" the available wires and, by this, reduces the size of the resulting circuit. Experimental evaluations based on established reversible and fault-tolerant quantum circuits confirm that the proposed solution reduces the amount of wires by more than 90% compared to unoptimized quantum circuits.

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arXiv2016

Performing Quantum Computing Experiments in the Cloud

Quantum computing technology has reached a second renaissance in the past five years. Increased interest from both the private and public sector combined with extraordinary theoretical and experimental progress has solidified this technology as a major advancement in the 21st century. As anticipated by many, the first realisation of quantum computing technology would occur over the cloud, with users logging onto dedicated hardware over the classical internet. Recently IBM has released the {\em Quantum Experience} which allows users to access a five qubit quantum processor. In this paper we take advantage of this online availability of actual quantum hardware and present four quantum information experiments that have never been demonstrated before. We utilise the IBM chip to realise protocols in Quantum Error Correction, Quantum Arithmetic, Quantum graph theory and Fault-tolerant quantum computation, by accessing the device remotely through the cloud. While the results are subject to significant noise, the correct results are returned from the chip. This demonstrates the power of experimental groups opening up their technology to a wider audience and will hopefully allow for the next stage development in quantum information technology.

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arXiv2016

Local and Distributed Quantum Computation

Experimental groups are now fabricating quantum processors powerful enough to execute small instances of quantum algorithms and definitively demonstrate quantum error correction that extends the lifetime of quantum data, adding urgency to architectural investigations. Although other options continue to be explored, effort is coalescing around topological coding models as the most practical implementation option for error correction on realizable microarchitectures. Scalability concerns have also motivated architects to propose distributed memory multicomputer architectures, with experimental efforts demonstrating some of the basic building blocks to make such designs possible. We compile the latest results from a variety of different systems aiming at the construction of a scalable quantum computer.

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arXiv2016

Synthesis of Arbitrary Quantum Circuits to Topological Assembly

Given a quantum algorithm, it is highly nontrivial to devise an efficient sequence of physical gates implementing the algorithm on real hardware and incorporating topological quantum error correction. In this paper, we present a first step towards this goal, focusing on generating correct and simple arrangements of topological structures that correspond to a given quantum circuit and largely neglecting their efficiency. We detail the many challenges that will need to be tackled in the pursuit of efficiency. The software source code can be consulted at https://github.com/alexandrupaler/tqec.

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arXiv2015

A Regular Representation of Quantum Circuits

We present a quantum circuit representation consisting entirely of qubit initialisations (I), a network of controlled-NOT gates (C) and measurements with respect to different bases (M). The ICM representation is useful for optimisation of quantum circuits that include teleportation, which is required for fault-tolerant, error corrected quantum computation. The non-deterministic nature of teleportation necessitates the conditional introduction of corrective quantum gates and additional ancillae during circuit execution. Therefore, the standard optimisation objectives, gate count and number of wires, are not well-defined for general teleportation-based circuits. The transformation of a circuit into the ICM representation provides a canonical form for an exact fault-tolerant, error corrected circuit needed for optimisation prior to the final implementation in a realistic hardware model.

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arXiv2015

An introduction to Fault-tolerant Quantum Computing

In this paper we provide a basic introduction of the core ideas and theories surrounding fault-tolerant quantum computation. These concepts underly the theoretical framework of large-scale quantum computation and communications and are the driving force for many recent experimental efforts to construct small to medium sized arrays of controllable quantum bits. We examine the basic principals of redundant quantum encoding, required to protect quantum bits from errors generated from both imprecise control and environmental interactions and then examine the principals of fault-tolerance from largely a classical framework. As quantum fault-tolerance essentially is avoiding the uncontrollable cascade of errors caused by the interaction of quantum-bits, these concepts can be directly mapped to quantum information.

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