arXiv subjects

Simon Klix

Publications and source records attributed to Simon Klix.

3 recordsLinked to original sources

arXiv2026

SoK: From Silicon to Netlist and Beyond $-$ Two Decades of Hardware Reverse Engineering Research

Hardware serves as the root of trust in modern computing systems, making Hardware Reverse Engineering (HRE) essential for security assurance$-$from design verification and supply-chain integrity to vulnerability discovery. We scope HRE to netlist recovery and its subsequent analysis, spanning the three subdomains of Integrated Circuit (IC), Field-Programmable Gate Array (FPGA), and netlist reverse engineering. These subdomains differ in their methodologies, but share core processes and are shaped by common requirements and legal constraints of the same stakeholders. Despite an increasing number of publications, the field lacks a systematic understanding of how these obstacles have stunted the research ecosystem. To address this gap, we present the first large-scale Systematization of Knowledge (SoK) of the HRE workflow, analyzing 187 peer-reviewed publications. Across all three subdomains, we identify eleven concrete technical challenges$-$from a widening gap between academic research and modern semiconductor technology nodes to overly idealized assumptions in netlist analysis$-$and propose actionable directions for each. A retrospective evaluation of all 30 published artifacts reveals that key results could be reproduced for only seven, a mere 4 % of all 187 papers in our corpus, confirming a systemic reproducibility crisis. We trace both the technical and reproducibility challenges to three structural barriers that recur across all subdomains: scarce reusable artifacts, missing benchmarks, and unresolved legal constraints on data sharing and collaboration. Based on these findings, we derive stakeholder-specific recommendations for academia, industry, and government to transition HRE from isolated research silos toward a collaborative discipline capable of assuring increasingly complex, global hardware supply chains.

cs.CR↗

arXiv2025

HAL -- An Open-Source Framework for Gate-Level Netlist Analysis

HAL is an open-source framework for gate-level netlist analysis, an integral step in hardware reverse engineering. It provides analysts with an interactive GUI, an extensible plugin system, and APIs in both C++ and Python for rapid prototyping and automation. In addition, HAL ships with plugins for word-level modularization, cryptographic analysis, simulation, and graph-based exploration. Since its release in 2019, HAL has become widely adopted in academia, industry, government, and teaching. It underpins at least 23 academic publications, is taught in hands-on trainings, conference tutorials, and university classes, and has collected over 680 stars and 86 forks on GitHub. By enabling accessible and reproducible hardware reverse engineering research, HAL has significantly advanced the field and the understanding of real-world capabilities and threats.

cs.CR↗

arXiv2023

Stealing Maggie's Secrets -- On the Challenges of IP Theft Through FPGA Reverse Engineering

Intellectual Property (IP) theft is a cause of major financial and reputational damage, reportedly in the range of hundreds of billions of dollars annually in the U.S. alone. Field Programmable Gate Arrays (FPGAs) are particularly exposed to IP theft, because their configuration file contains the IP in a proprietary format that can be mapped to a gate-level netlist with moderate effort. Despite this threat, the scientific understanding of this issue lacks behind reality, thereby preventing an in-depth assessment of IP theft from FPGAs in academia. We address this discrepancy through a real-world case study on a Lattice iCE40 FPGA found inside iPhone 7. Apple refers to this FPGA as Maggie. By reverse engineering the proprietary signal-processing algorithm implemented on Maggie, we generate novel insights into the actual efforts required to commit FPGA IP theft and the challenges an attacker faces on the way. Informed by our case study, we then introduce generalized netlist reverse engineering techniques that drastically reduce the required manual effort and are applicable across a diverse spectrum of FPGA implementations and architectures. We evaluate these techniques on six benchmarks that are representative of different FPGA applications and have been synthesized for Xilinx and Lattice FPGAs, as well as in an end-to-end white-box case study. Finally, we provide a comprehensive open-source tool suite of netlist reverse engineering techniques to foster future research, enable the community to perform realistic threat assessments, and facilitate the evaluation of novel countermeasures.

cs.CR↗