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Simona K. Grigorova

Publications and source records attributed to Simona K. Grigorova.

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When More Becomes Less: Topology-Reversed Three-Qubit Gate Performance on IBM Quantum Processors

The exact Toffoli gate admits a six-CX decomposition, denoted by $CCX_6$, that is optimal under unrestricted two-qubit connectivity. On a linear three-qubit topology, however, $CCX_6$ contains 4 nearest-neighbor CX gates and 2 non-nearest-neighbor CX gates. By contrast, an alternative exact decomposition, denoted by $CCX_8$, uses only 8 nearest-neighbor CX gates. Because CCX is locally equivalent to CCZ, we perform the experiments using the corresponding $\cczs$ and $\cczl$ circuits. We compare these circuits on sampled linear triples of the 156-qubit IBM Quantum Heron processors \texttt{ibm\_fez} and \texttt{ibm\_kingston}. Under the compilation protocol, the nominal $\cczs$ circuit becomes a twelve-CZ implementation, whereas the linear-nearest-neighbor circuit retains eight native CZ gates. Experimentally measured ensemble-feature-selection estimates favor the eight-CZ realization on nearly all retained triples. We test the same ordering by preparing a three-qubit hypergraph state, which probes the coherent conditional phase rather than only computational-basis populations. The measured hypergraph-state infidelity is lower for the $\cczl$ circuit for most triples on both processors. Phase-altered interleaved randomized benchmarking provides a complementary comparison of Clifford surrogates preserving the two compiled entangling structures. Within the scope of the tested circuits and phase-sensitive input state, the results demonstrate that hardware connectivity can reverse the operational ranking of exact decompositions: a circuit with more abstract two-qubit gates can yield the better physical implementation.

quant-ph

Phase-Altered Interleaved Randomized Benchmarking for Compiled Quantum Gates

Interleaved randomized benchmarking (IRB) provides a scalable estimate of a gate's error rate, but its standard guarantees require the interleaved gate to be Clifford~\cite{Magesan2012Interleaved,magesan2012characterizing}. In superconducting processors, many non-Clifford phase gates in compiled circuits are implemented virtually as software-defined frame updates rather than as additional control pulses~\cite{mckay2017efficient}. This raises the question of whether inserting or removing such virtual phases measurably changes IRB error estimates. We introduce \emph{phase-altered interleaved randomized benchmarking} (PA-IRB), a paired-IRB diagnostic protocol comparing phase-stripped and phase-dressed Clifford interleaving gates derived from the same compiled implementation. PA-IRB reports $Δr=r_d-r_s$ with combined uncertainty to test whether virtual phase gates affect the extracted IRB decay beyond statistical error. As a case study, we apply PA-IRB to a compiled Toffoli gate executed on IBM superconducting processors, where the constituent $T/T^\dagger$ gates are implemented as virtual $Z$ rotations. Across tested calibration runs, $Δr$ is consistent with zero within uncertainty, indicating that virtual phase addition or removal does not measurably alter the IRB-derived error estimate under the employed compilation and execution stack. More generally, PA-IRB provides a lightweight, abstraction-aware diagnostic for benchmarking workflows involving software-defined phase operations. The same paired comparison can also be used to place operational bounds on the contribution of non-Clifford components to the compiled gate error, even when those components are physically executed rather than implemented virtually.

quant-ph