arXiv subjects

Siqing Fu

Publications and source records attributed to Siqing Fu.

4 recordsLinked to original sources

arXiv2026

NeuroPDE+: A Scalable Neuromorphic PDE Accelerator Based on Spintronic and Ferroelectric Devices

The pursuit of high-performance PDE solvers rests on three fundamental challenges: (i) the curse of dimensionality in kinetic and financial equations, (ii) the poor extrapolation of purely data-driven surrogates, and (iii) the widening gap between algorithm design and hardware specialization. To overcome these challenges, we present NeuroPDE+, a scalable neuromorphic PDE solver design based on spintronic and ferroelectric devices for accelerating PDE solutions. NeuroPDE+ consists of two dedicated units: a diffusion tracking unit (DTU), which emulates random walks on Markov chains through activations between hardware neurons, and a scattering tracking unit (STU), which samples non-local jumps via a multi-level probability tree. System-level simulations suggest that NeuroPDE+ achieves a squared error below 1e-2 in steady-state heat equation and particle transport problems. Simulation results further indicate that the DTU achieves up to a 315x performance gain over previous neuromorphic processors, and that the STU achieves a 1000x speedup compared to a general-purpose CPU. Co-designing algorithm and hardware with intrinsic stochasticity and non-volatile in-memory computing, NeuroPDE+ preliminarily explores a new paradigm for efficient and scalable neuromorphic PDE solvers. This approach could pave the way for probabilistic computing architectures in large-scale scientific simulations.

cs.AR↗

arXiv2025

NeuroPDE: A Neuromorphic PDE Solver Based on Spintronic and Ferroelectric Devices

In recent years, new methods for solving partial differential equations (PDEs) such as Monte Carlo random walk methods have gained considerable attention. However, due to the lack of hardware-intrinsic randomness in the conventional von Neumann architecture, the performance of PDE solvers is limited. In this paper, we introduce NeuroPDE, a hardware design for neuromorphic PDE solvers that utilizes emerging spintronic and ferroelectric devices. NeuroPDE incorporates spin neurons that are capable of probabilistic transmission to emulate random walks, along with ferroelectric synapses that store continuous weights non-volatilely. The proposed NeuroPDE achieves a variance of less than 1e-2 compared to analytical solutions when solving diffusion equations, demonstrating a performance advantage of 3.48x to 315x speedup in execution time and an energy consumption advantage of 2.7x to 29.8x over advanced CMOS-based neuromorphic chips. By leveraging the inherent physical stochasticity of emerging devices, this study paves the way for future probabilistic neuromorphic computing systems.

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arXiv2024

Spin-NeuroMem: A Low-Power Neuromorphic Associative Memory Design Based on Spintronic Devices

Biologically-inspired computing models have made significant progress in recent years, but the conventional von Neumann architecture is inefficient for the large-scale matrix operations and massive parallelism required by these models. This paper presents Spin-NeuroMem, a low-power circuit design of Hopfield network for the function of associative memory. Spin-NeuroMem is equipped with energy-efficient spintronic synapses which utilize magnetic tunnel junctions (MTJs) to store weight matrices of multiple associative memories. The proposed synapse design achieves as low as 17.4% power consumption compared to the state-of-the-art synapse designs. Spin-NeuroMem also encompasses a novel voltage converter with a 53.3% reduction in transistor usage for effective Hopfield network computation. In addition, we propose an associative memory simulator for the first time, which achieves a 5Mx speedup with a comparable associative memory effect. By harnessing the potential of spintronic devices, this work paves the way for the development of energy-efficient and scalable neuromorphic computing systems.

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arXiv2023

RHS-TRNG: A Resilient High-Speed True Random Number Generator Based on STT-MTJ Device

High-quality random numbers are very critical to many fields such as cryptography, finance, and scientific simulation, which calls for the design of reliable true random number generators (TRNGs). Limited by entropy source, throughput, reliability, and system integration, existing TRNG designs are difficult to be deployed in real computing systems to greatly accelerate target applications. This study proposes a TRNG circuit named RHS-TRNG based on spin-transfer torque magnetic tunnel junction (STT-MTJ). RHS-TRNG generates resilient and high-speed random bit sequences exploiting the stochastic switching characteristics of STT-MTJ. By circuit/system co-design, we integrate RHS-TRNG into a RISC-V processor as an acceleration component, which is driven by customized random number generation instructions. Our experimental results show that a single cell of RHS-TRNG has a random bit generation speed of up to 303 Mb/s, which is the highest among existing MTJ-based TRNGs. Higher throughput can be achieved by exploiting cell-level parallelism. RHS-TRNG also shows strong resilience against PVT variations thanks to our designs using bidirectional switching currents and dual generator units. In addition, our system evaluation results using gem5 simulator suggest that the system equipped with RHS-TRNG can achieve 3.4-12x higher performance in speeding up option pricing programs than software implementations of random number generation.

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