arXiv subjects

Smruti R. Sarangi

Publications and source records attributed to Smruti R. Sarangi.

23 records · Page 2Linked to original sources

arXiv2017

Sensitivity Analysis of Core Specialization Techniques

The instruction footprint of OS-intensive workloads such as web servers, database servers, and file servers typically exceeds the size of the instruction cache (32 KB). Consequently, such workloads incur a lot of i-cache misses, which reduces their performance drastically. Several papers have proposed to improve the performance of such workloads using core specialization. In this scheme, tasks with different instruction footprints are executed on different cores. In this report, we study the performance of five state of the art core specialization techniques: SelectiveOffload [6], FlexSC [8], DisAggregateOS [5], SLICC [2], and SchedTask [3] for different system parameters. Our studies show that for a suite of 8 popular OS-intensive workloads, SchedTask performs best for all evaluated configurations.

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arXiv2015

A Wait-Free Stack

In this paper, we describe a novel algorithm to create a con- current wait-free stack. To the best of our knowledge, this is the first wait-free algorithm for a general purpose stack. In the past, researchers have proposed restricted wait-free implementations of stacks, lock-free implementations, and efficient universal constructions that can support wait-free stacks. The crux of our wait-free implementation is a fast pop operation that does not modify the stack top; instead, it walks down the stack till it finds a node that is unmarked. It marks it but does not delete it. Subsequently, it is lazily deleted by a cleanup operation. This operation keeps the size of the stack in check by not allowing the size of the stack to increase beyond a factor of W as compared to the actual size. All our operations are wait-free and linearizable.

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arXiv2015

Fundamental Results for a Generic Implementation of Barriers using Optical Interconnects

In this report, we report some fundamental results and bounds on the number of messages and storage required to implement barriers using futuristic on-chip optical and RF networks. We prove that it is necessary to maintain a count to at least N (number of threads) in memory, broadcast the barrier id at least once, and if we elect a co-ordinator, we can reduce the number of messages by a factor of O(N ).

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arXiv2015

Tejas Simulator : Validation against Hardware

In this report we show results that validate the Tejas architectural simulator against native hardware. We report mean error rates of 11.45% and 18.77% for the SPEC2006 and Splash2 benchmark suites respectively. These error rates are competitive and in most cases better than the numbers reported by other contemporary simulators.

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arXiv2014

Three Experiments to Analyze the Nature of the Heat Spreader

In this paper, we describe ongoing work to investigate the properties of the heat spreader, and its implication on architecture research. In specific, we conduct two experiments to quantify the heat distribution across the surface of a spreader during normal operation. The first experiment uses T-type thermocouples, to find the temperature difference across different points on the spreader. We observe about a 6 degree celsius temperature difference on average. In the second experiment, we try to capture the temperature gradients using an infrared camera. However, this experiment was inconclusive because of some practical constraints such as the low emissivity of the spreader. We conclude that to properly model the spreader, it is necessary to conduct detailed finite element simulations. We describe a method to accurately measure the thermal conductivity of the heat spreader such that it can be used to compute the steady state temperature distribution across the spreader.

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