Sohaib Majzoub | Searcharxiv

arXiv2026

Inversion of Electrochemical Immittance Spectra based on the Mellin Transform

In this work, we show that the Fredholm integral equations underlying the distribution of relaxation times (DRT), the distribution of capacitive times (DCT), and related frameworks share a common mathematical structure, namely that of a Mellin convolution. This comes from the fact that all standard immittance (impedance or admittance) kernels depend on the product $\omega\tau$ rather than on $\omega$ and $\tau$ independently. Exploiting this structure, we derive an exact algebraic inversion formula in Mellin space that converts the deconvolution problem into a closed-form relation between the Mellin transform of the measured immittance and that of the unknown distribution function. The framework is validated analytically on a set of examples including the constant phase element (CPE), the Davidson-Cole (DC) model, and the finite-length Warburg model with blocking boundary conditions. It is also validated numerically using the fast Mellin transform via the fast Fourier transform algorithm for both the CPE and the DC model, including their DRT and DCT recovery under clean and noisy conditions. The approach unifies the impedance- and admittance-based inversions under a single spectral framework, and provides a new approach for the characterization of electrochemical systems from immittance data.

physics.app-ph↗

arXiv2024

Using Intermittent Chaotic Clocks to Secure Cryptographic Chips

This letter proposes using intermittent chaotic clocks, generated from chaotic maps, to drive cryptographic chips running the Advanced Encryption Standard as a countermeasure against Correlation Power Analysis attacks. Five different chaotic maps -- namely: the Logistic map, the Bernoulli shift map, the Henon map, the Tent map, and the Ikeda map -- are used in this work to generate chaotic clocks. The performance of these chaotic clocks is evaluated in terms of timing overhead and the resilience of the driven chip against Correlation Power Analysis attacks. All proposed chaotic clocking schemes successfully protect the driven chip against attacks, with the clocks produced by the optimized Ikeda, Henon, and Logistic maps achieving the lowest timing overhead. These optimized maps, due to their intermittent chaotic behavior, exhibit lower timing overhead compared to previous work. Notably, the chaotic clock generated by the optimized Ikeda map approaches the theoretical limit of timing overhead, i.e., half the execution time of a reference periodic clock.

nlin.CD↗