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Soham Chakraborty

Publications and source records attributed to Soham Chakraborty.

At least 19 recordsLinked to original sources
arXiv2026

Non-uniqueness of continuous trace-scaling flows on certain full factors

We show that if M is a full II_infinity factor such that the fundamental group of a finite corner is R and Out(M) is a locally compact second countable group, then M admits either a unique continuous trace scaling flow or a continuum of pairwise distinct ones, up to cocycle conjugacy. Equivalently, there is either a unique III_1 factor or a continuum of pairwise non-isomorphic III_1 factors with continuous core M. We apply this dichotomy result to factors constructed in [Dep12] and [Cha25] where Out(M) is a Lie group. We also give two independent constructions of full factors admitting a continuum of pairwise distinct trace-scaling flows where the outer automorphism group is unknown.

math.OA↗
arXiv2026

On essential freeness of actions of mixed identity-free groups

It was asked in [ACTT23] if every faithful, discrete, ergodic pmp action of a mixed identity-free (MIF) group is essentially free. In this short note we give some positive evidence by showing that for a MIF group, any faithful generalized Bernoulli action and any affine action on a compact abelian group is essentially free. This gives some classes of discrete ergodic actions with this property beyond the totally ergodic or compact case.

math.DS↗
arXiv2026

Large-Signal Stability Analysis of Optimization-Based Secondary Control for Distributed Energy Resources

This article develops a large-signal stability analysis for a sampled-data optimization-based secondary controller for distributed energy resources (DERs) in power systems. The induced closed loop combines nonlinear inverter power-flow dynamics, filtered active and reactive power measurements, constrained optimization updates, and interpolation-based actuation between sampling instants. We study this optimization-in-the-loop nonlinear sampled-data system beyond local linearization. The analysis provides computable bounds on the voltage, filtered reactive power, and the secondary control input. We further characterize steady-state operating points and establish how the optimizer objectives and constraints connect voltage regulation with equal per-unitized reactive power sharing. Finally, input-to-state stability of the frequency dynamics is established with respect to DER voltages and control inputs. These results provide a rigorous mathematical foundation for sampled-data optimization-based secondary control of DERs.

eess.SY↗
arXiv2026

GraphAlg Playground: An Online Platform for Learning and Experimenting with the GraphAlg Language

The GraphAlg language for graph algorithms enables native support for user-defined graph analytics workloads in databases. In this demonstration, we present a web-based playground for writing and executing GraphAlg programs in the web browser, including an interactive tutorial explaining its key concepts. The playground runs inside the user's web browser without any installation, and is freely available under a permissive license as a reusable library. We present two demonstration scenarios of the publicly available playground website, showing how new users can learn to program in GraphAlg using the tutorial, while expert users can use the playground to prototype and validate their algorithms.

cs.DB↗
arXiv2026

Deductive Verification of Weak Memory Programs with View-based Protocols (extended version)

Concurrent programming under weak memory concurrency faces substantial challenges to ensure correctness due to program behaviors that cannot be explained by thread interleaving, a.k.a. sequential consistency. While several program logics are proposed to reason about weak memory concurrency, their usage has been limited to intricate manual proofs. On the other hand, the VerCors verifier provides a rich toolset for automated deductive verification for sequential consistency. In this paper, we bridge this gap for automated deductive verification of weak memory concurrent programs with the VerCors deductive verification tool. We propose an approach to encode weak memory concurrency in VerCors. We develop VerCors-relaxed, where we extend the VerCors atomics support and bring concepts from several protocol automata to encode permission-based separation logics for weak memory concurrency models. To demonstrate the effectiveness of our approach, we encode the relaxed fragment of the SLR program logic, a recent state-of-the-art permission-based separation logic for weak memory concurrency in VerCors-relaxed, our extension of VerCors. We use the SLR encoding on VerCors-relaxed to automatically verify several examples from the literature within realistic performance.

cs.LO↗
arXiv2026

Algorithm Support for Graph Databases, Done Right

Graph database query languages cannot express algorithms like PageRank, forcing costly data wrangling, while existing solutions such as algorithm libraries, vertex-centric APIs, and recursive CTEs lack the necessary combination of expressiveness, performance, and usability. We present GraphAlg: a domain-specific language for graph algorithms that compiles to relational algebra, enabling seamless integration with query processing pipelines. Built on linear algebra foundations, GraphAlg provides intuitive matrix operations that are amenable to aggressive optimization including sparsity analysis, loop-invariant code motion, and in-place aggregation. Our implementation in AvantGraph demonstrates significant code complexity reduction compared to SQL/Python and Pregel while achieving excellent performance on LDBC Graphalytics benchmarks. GraphAlg establishes that graph databases can serve as unified platforms for both queries and analytics.

cs.DB↗
arXiv2025

Measured inverse semigroups and their actions on von Neumann algebras and equivalence relations

It is known to experts that certain regular inclusions of von Neumann algebras arise as crossed products with cocycle actions of the canonical quotient groupoids associated with the inclusions. Similarly, `strongly normal' inclusions of standard equivalence relations arise as semi-direct products with cocycle actions of the quotient groupoids. However, to the author's knowledge, rigorous proofs of these results in full generality are absent in the literature. In this article, we exploit the usual correspondence between inverse semigroups and groupoids, and give a unified approach to proving these `folklore' results and fill this gap in the literature.

math.OA↗
arXiv2025

Measured groupoids beyond equivalence relations and group actions

We construct the first examples of genuine ergodic discrete measured groupoids that are not isomorphic to any equivalence relation or transformation groupoid. We use a construction due to B.H. Neumann of an uncountable family of pairwise non-isomorphic 2-generated groups for our result.

math.GR↗
arXiv2025

GPUMC: A Stateless Model Checker for GPU Weak Memory Concurrency

GPU computing is embracing weak memory concurrency for performance improvement. However, compared to CPUs, modern GPUs provide more fine-grained concurrency features such as scopes, have additional properties like divergence, and thereby follow different weak memory consistency models. These features and properties make concurrent programming on GPUs more complex and error-prone. To this end, we present GPUMC, a stateless model checker to check the correctness of GPU shared-memory concurrent programs under scoped-RC11 weak memory concurrency model. GPUMC explores all possible executions in GPU programs to reveal various errors - races, barrier divergence, and assertion violations. In addition, GPUMC also automatically repairs these errors in the appropriate cases. We evaluate GPUMC with benchmarks and real-life GPU programs. GPUMC is efficient both in time and memory in verifying large GPU programs where state-of-the-art tools are timed out. In addition, GPUMC identifies all known errors in these benchmarks compared to the state-of-the-art tools.

cs.LO↗
arXiv2025

RadarTrack: Enhancing Ego-Vehicle Speed Estimation with Single-chip mmWave Radar

In this work, we introduce RadarTrack, an innovative ego-speed estimation framework utilizing a single-chip millimeter-wave (mmWave) radar to deliver robust speed estimation for mobile platforms. Unlike previous methods that depend on cross-modal learning and computationally intensive Deep Neural Networks (DNNs), RadarTrack utilizes a novel phase-based speed estimation approach. This method effectively overcomes the limitations of conventional ego-speed estimation approaches which rely on doppler measurements and static surrondings. RadarTrack is designed for low-latency operation on embedded platforms, making it suitable for real-time applications where speed and efficiency are critical. Our key contributions include the introduction of a novel phase-based speed estimation technique solely based on signal processing and the implementation of a real-time prototype validated through extensive real-world evaluations. By providing a reliable and lightweight solution for ego-speed estimation, RadarTrack holds significant potential for a wide range of applications, including micro-robotics, augmented reality, and autonomous navigation.

cs.RO↗
arXiv2024

Cage: Hardware-Accelerated Safe WebAssembly

WebAssembly (WASM) is an immensely versatile and increasingly popular compilation target. It executes applications written in several languages (e.g., C/C++) with near-native performance in various domains (e.g., mobile, edge, cloud). Despite WASM's sandboxing feature, which isolates applications from other instances and the host platform, WASM does not inherently provide any memory safety guarantees for applications written in low-level, unsafe languages. To this end, we propose Cage, a hardware-accelerated toolchain for WASM that supports unmodified applications compiled to WASM and utilizes diverse Arm hardware features aiming to enrich the memory safety properties of WASM. Precisely, Cage leverages Arm's Memory Tagging Extension (MTE) to (i) provide spatial and temporal memory safety for heap and stack allocations and (ii) improve the performance of WASM's sandboxing mechanism. Cage further employs Arm's Pointer Authentication (PAC) to prevent leaked pointers from being reused by other WASM instances, thus enhancing WASM's security properties. We implement our system based on 64-bit WASM. We provide a WASM compiler and runtime with support for Arm's MTE and PAC. On top of that, Cage's LLVM-based compiler toolchain transforms unmodified applications to provide spatial and temporal memory safety for stack and heap allocations and prevent function pointer reuse. Our evaluation on real hardware shows that Cage incurs minimal runtime (<5.8%) and memory (<3.7%) overheads and can improve the performance of WASM's sandboxing mechanism, achieving a speedup of over 5.1%, while offering efficient memory safety guarantees.

cs.PL↗
arXiv2024

Factoriality of groupoid von Neumann algebras

We give a characterisation of factoriality of the groupoid von Neumann algebra $L(\mathcal{G})$ associated to a discrete measured groupoid $(\mathcal{G},μ)$. We introduce the notion of groupoids with `infinite conjugacy classes' and show that this property together with ergodicity of the groupoid is equivalent to factoriality of $L(\mathcal{G})$.

math.OA↗
arXiv2024

A Distributed Malicious Agent Detection Scheme for Resilient Power Apportioning in Microgrids

We consider the framework of distributed aggregation of Distributed Energy Resources (DERs) in power networks to provide ancillary services to the power grid. Existing aggregation schemes work under the assumption of trust and honest behavior of the DERs and can suffer when that is not the case. In this article, we develop a distributed detection scheme that allows the DERs to detect and isolate the maliciously behaving DERs. We propose a model for the maliciously behaving DERs and show that the proposed distributed scheme leads to the detection of the malicious DERs. Further, augmented with the distributed power apportioning algorithm the proposed scheme provides a framework for resilient distributed power apportioning for ancillary service dispatch in power networks. A controller-hardware-in-the-loop (CHIL) experimental setup is developed to evaluate the performance of the proposed resilient distributed power apportioning scheme on an 8-commercial building distribution network (Central Core) connected to a 55 bus distribution network (External Power Network) based on the University of Minnesota Campus. A diversity of DERs and loads are included in the network to generalize the applicability of the framework. The experimental results corroborate the efficacy of the proposed resilient distributed power apportioning for ancillary service dispatch in power networks.

eess.SY↗
arXiv2024

A Plug and Play Distributed Secondary Controller for Microgrids with Grid-Forming Inverters

A distributed controller for secondary control problems in microgrids with grid-forming (GFM) inverter-based resources (IBRs) is developed. The controller is based on distributed optimization and is synthesized and implemented distributively enabling each GFM IBR to utilize decentralized measurements and the neighborhood information in the communication network. We present a convergence analysis establishing voltage regulation and reactive power sharing properties. A controller-hardware-in-the-loop experiment is conducted to evaluate the performance of the proposed controller. The experimental results corroborate the efficacy of the proposed distributed controller for secondary control.

eess.SY↗
arXiv2024

A type III$_1$ factor with the smallest outer automorphism group

The canonical modular homomorphism provides an embedding of $\mathbb{R}$ into the outer automorphism group Out($M$) of any type III$_{1}$ factor $M$. We provide an explicit construction of a full factor of type III$_{1}$ with separable predual such that the outer automorphism group is minimal, i.e. this embedding is an isomorphism. We obtain such a III$_{1}$ factor by using an amalgamated free product construction.

math.OA↗