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Sourav De

Publications and source records attributed to Sourav De.

9 recordsLinked to original sources

Convex Clustering Redefined: Robust Learning with the Median of Means Estimator

Clustering approaches that utilize convex loss functions have recently attracted growing interest in the formation of compact data clusters. Although classical methods like k-means and its wide family of variants are still widely used, all of them require the number of clusters k to be supplied as input, and many are notably sensitive to initialization. Convex clustering provides a more stable alternative by formulating the clustering task as a convex optimization problem, ensuring a unique global solution. However, it faces challenges in handling high-dimensional data, especially in the presence of noise and outliers. Additionally, strong fusion regularization, controlled by the tuning parameter, can hinder effective cluster formation within a convex clustering framework. To overcome these challenges, we introduce a robust approach that integrates convex clustering with the Median of Means (MoM) estimator, thus developing an outlier-resistant and efficient clustering framework that does not necessitate prior knowledge of the number of clusters. By leveraging the robustness of MoM alongside the stability of convex clustering, our method enhances both performance and efficiency, especially on large-scale datasets. Theoretical analysis demonstrates weak consistency under specific conditions, while experiments on synthetic and real-world datasets validate the method's superior performance compared to existing approaches.

stat.ML

CIMulator: A Comprehensive Simulation Platform for Computing-In-Memory Circuit Macros with Low Bit-Width and Real Memory Materials

This paper presents a simulation platform, namely CIMulator, for quantifying the efficacy of various synaptic devices in neuromorphic accelerators for different neural network architectures. Nonvolatile memory devices, such as resistive random-access memory, ferroelectric field-effect transistor, and volatile static random-access memory devices, can be selected as synaptic devices. A multilayer perceptron and convolutional neural networks (CNNs), such as LeNet-5, VGG-16, and a custom CNN named C4W-1, are simulated to evaluate the effects of these synaptic devices on the training and inference outcomes. The dataset used in the simulations are MNIST, CIFAR-10, and a white blood cell dataset. By applying batch normalization and appropriate optimizers in the training phase, neuromorphic systems with very low-bit-width or binary weights could achieve high pattern recognition rates that approach software-based CNN accuracy. We also introduce spiking neural networks with RRAM-based synaptic devices for the recognition of MNIST handwritten digits.

cs.NE

A Homogeneous Processing Fabric for Matrix-Vector Multiplication and Associative Search Using Ferroelectric Time-Domain Compute-in-Memory

In this work, we propose a ferroelectric FET(FeFET) time-domain compute-in-memory (TD-CiM) array as a homogeneous processing fabric for binary multiplication-accumulation (MAC) and content addressable memory (CAM). We demonstrate that: i) the XOR(XNOR)/AND logic function can be realized using a single cell composed of 2FeFETs connected in series; ii) a two-phase computation in an inverter chain with each stage featuring the XOR/AND cell to control the associated capacitor loading and the computation results of binary MAC and CAM are reflected in the chain output signal delay, illustrating full digital compatibility; iii) comprehensive theoretical and experimental validation of the proposed 2FeFET cell and inverter delay chains and their robustness against FeFET variation; iv) the homogeneous processing fabric is applied in hyperdimensional computing to show dynamic and fine-grain resource allocation to accommodate different tasks requiring varying demands over the binary MAC and CAM resources.

cs.ET

Alleviation of Temperature Variation Induced Accuracy Degradation in Ferroelectric FinFET Based Neural Network

This paper reports the impacts of temperature variation on the inference accuracy of pre-trained all-ferroelectric FinFET deep neural networks, along with plausible design techniques to abate these impacts. We adopted a pre-trained artificial neural network (N.N.) with 96.4% inference accuracy on the MNIST dataset as the baseline. As an aftermath of temperature change, a compact model captured the conductance drift of a programmed cell over a wide range of gate biases. We observed a significant inference accuracy degradation in the analog neural network at 233 K for an N.N. trained at 300 K. Finally, we deployed binary neural networks with "read voltage" optimization to ensure immunity of N.N. to accuracy degradation under temperature variation, maintaining an inference accuracy of 96%. Keywords: Ferroelectric memories

cs.LG

Neuromorphic Computing with Ferroelectric FinFETs in the Presence of Temperature, Process Variation, Device Aging and Flicker Noise

This paper reports a comprehensive study on the impacts of temperature-change, process variation, flicker noise and device aging on the inference accuracy of pre-trained all-ferroelectric (FE) FinFET deep neural networks. Multiple-level-cell (MLC) operation with a novel adaptive-program-and-read algorithm with 100ns write pulse has been experimentally demonstrated in 5 nm thick hafnium zirconium oxide (HZO)-based FE-FinFET. With pre-trained neural network (NN) with 97.5% inference accuracy on MNIST dataset as baseline, device to device variation is shown to have negligible impact. Flicker noise characterization at various bias conditions depicts that drain current fluctuation is less than 0.7% with virtually no inference accuracy degradation. The conductance drift of a programmed cell, as an aftermath of temperature change, was captured by a compact model over a wide range of gate biases. Despite significant inference accuracy degradation at 233K for a NN trained at 300K, gate bias optimization for recovering the accuracy is demonstrated. Endurance above 10$^8$ cycles and extrapolated retention above 10 years are shown, which paves the way for edge device artificial intelligence with FE-FinFETs.

cs.ET

Stochastic Variations in Nanoscale HZO based Ferroelectric finFETs: A Synergistic Approach of READ Optimization and Hybrid Precision Mixed Signal WRITE Operation to Mitigate the Implications on DNN Applications

This paper reports a synergistic approach of READ and WRITE optimization by deploying a high-precision digital computation unit along with a low-precision ferroelectric finFET (Fe-finFETs) based analog vector-matrix multiplication block for mitigating the impact of stochastic device variations in hafnium zirconium oxide (HZO) based Fe-finFETs.

physics.app-ph

Analytical Modelling of Ferroelectricity Instigated Enhanced Electrostatic Control in Short-Channel FinFETs

This study simulated negative-capacitance double gate FinFETs with channel lengths ranging from 25nm to 100nm using TCAD. The results show that negative capacitance significantly reduces subthreshold swing as well as drain induced barrier lowering effects. The improvement is found to be significantly more prominent for short channel devices than long ones, which demonstrates the tremendous advantage of negative capacitance gate stack for scaled MOSFETs. A compact analytical formulation is developed to quantify sub-threshold swing improvement for short channel devices.

physics.app-ph

Formation of Uniform Crystal and Reduction of Electrical Variation in HfZrO$_2$ Ferroelectric Memory by Thermal Engineering

In this paper we proclaim excellent variation control in Hf$_{0.5}$Zr$_{0.5}$O$_2$ based ferroelectric films obtained by germination of large ferroelectric domain via extended duration of thermal annealing. 10nm thick Hf$_{0.5}$Zr$_{0.5}$O$_2$ based ferroelectric capacitors with TiN as bottom and top electrodes are fabricated and characterized. The duration of rapid thermal annealing (RTA) is varied to observe its effect on crystal formation and device electrical properties at 700C. The device to device variation in terms of coercive voltage and peak capacitance are reduced from 0.4V to 0.01V and from 2*$10^{-5}$nF/cm$^2$ to 4*$10^{-6}$nF/cm$^2$, respectively, by increasing the RTA duration. High resolution transmission electron micrograph clearly shows large and uniform ferroelectric domains with RTA of 180 seconds. Extended duration of RTA likely allows uniform crystal to form, which mitigates the stochasticity of the distribution of ferroelectric and paraelectric domains, and deterministic switching has been infused. This improvement paves the way for implementing Hf$_{0.5}$Zr$_{0.5}$O$_2$ based deeply scaled devices for memory and steep slope device applications.

physics.app-ph

A computationally efficient compact model for ferroelectric FETs for the simulation of online training of neural networks

Tri-gate ferroelectric FETs with Hf0.5Zr0.5O2 gate insulator for memory and neuromorphic applications are fabricated and characterized for multi-level operation. The conductance and threshold voltage exhibit highly linear and symmetric characteristics. A compact analytical model is developed to accurately capture FET transfer characteristics, including series resistance, coulombic scattering, and vertical field dependent mobility degradation effects, as well as the evolvement of threshold voltage and mobility with ferroelectric polarization switching. The model covers both sub-threshold and strong inversion operation. Additional measurements confirm ferroelectric switching as opposed to carrier-trapping-based memory operation. The compact model is implemented in a simulation platform for online training of deep neural networks.

physics.app-ph