arXiv subjects

Stefan Wiefels

Publications and source records attributed to Stefan Wiefels.

3 recordsLinked to original sources

arXiv2026

OTTER - Two Transistor - One RRAM Architecture for Reliable In-Memory-Computing in 28 nm CMOS Technology

This work presents OTTER, a 28 nm CMOS platform co-integrated with TaOx-based valence-change mechanism (VCM) RRAM, demonstrating a two-transistor-one-memristive-device (2T1R) architecture for reliable in-memory computing. The 2T1R cell combines a low-drive-current (LD) transistor and a high-drive-current (HD) transistor in parallel, providing dedicated bias paths for SET programming and RESET operation, respectively. Through systematic experimental and simulated comparison of various transistor-pairing configurations using the physical compact model JART VCM Rth, design guidelines for transistor sizing are derived, establishing the minimum RESET transistor W/L required for complete RESET as a function of the SET current compliance. The 2T1R cell is further characterized under pulse-based programming, demonstrating multilevel analog conductance tuning with narrow, well separated conductance states across six programmable levels. An analog content-addressable memory (aCAM) design based on the same 2T1R cell is additionally analyzed at the circuit level, evaluating trade-offs between top- and bottom-connected RRAM comparator configurations. A hardware implementation of compute-in-memory (CIM) multiply-and-accumulate (MAC) operations is further demonstrated on a 15 x 15 2T1R crossbar array.

cs.ET↗

arXiv2024

Roadmap to Neuromorphic Computing with Emerging Technologies

The roadmap is organized into several thematic sections, outlining current computing challenges, discussing the neuromorphic computing approach, analyzing mature and currently utilized technologies, providing an overview of emerging technologies, addressing material challenges, exploring novel computing concepts, and finally examining the maturity level of emerging technologies while determining the next essential steps for their advancement.

eess.SP↗

arXiv2021

Intrinsic RESET speed limit of valence change memories

During the last decade, valence change memory (VCM) has been extensively studied due to its promising features, such as a high endurance and fast switching times. The information is stored in a high resistive state (logcial '0', HRS) and a low resistive state (logcial '1', LRS). It can also be operated in two different writing schemes, namely a unipolar switching mode (LRS and HRS are written at the same voltage polarity) and a bipolar switching mode (LRS and HRS are written at opposite voltage polarities). VCM, however, still suffers from a large variability during writing operations and also faults occur, which are not yet fully understood and, therefore, require a better understanding of the underlying fault mechanisms. In this study, a new intrinsic failure mechanism is identified, which prohibits RESET times (transition from LRS to HRS) faster than 400 ps and possibly also limits the endurance. We demonstrate this RESET speed limitation by measuring the RESET kinetics of two valence change memory devices (namely Pt/TaO$_\mathrm{x}$/Ta and Pt/ZrO$_\mathrm{x}$/Ta) in the time regime from 50 ns to 50 ps, corresponding to the fastest writing time reported for VCM. Faster RESET times were achieved by increasing the applied pulse voltage. Above a voltage threshold it was, however, no longer possible to reset both types of devices. Instead a unipolar SET (transition from HRS to LRS) event occurred, preventing faster RESET times. The occurrence of the unipolar SET is attributed to an oxygen exchange at the interface to the Pt~electrode, which can be suppressed by introducing an oxygen blocking layer at this interface, which also allowed for 50 ps fast RESET times.

physics.app-ph↗