arXiv subjects

Stefan van Waasen

Publications and source records attributed to Stefan van Waasen.

15 recordsLinked to original sources

arXiv2026

Hybrid neural denoising for resource-efficient near- and sub-threshold radio triggering of extensive air showers

Autonomous radio self-triggering for extensive air showers requires strong rejection of radio-frequency interference while preserving weak pulses within station-level hardware constraints. We present a hybrid neural trigger comprising a compact waveform denoiser followed by a classifier. The method is evaluated using experimentally measured high-interference background traces and detector-folded simulated air-shower pulses produced with the Pierre Auger Offline chain, with the benchmark concentrated in the near-threshold regime. Hardware constraints are incorporated through hyperparameter optimisation, quantisation-aware training, and high-granularity fixed-point quantisation. Applying the conventional peak-envelope trigger after denoising increases its area under the receiver-operating-characteristic curve from 0.63 to 0.98. At a false-positive rate of 10^-4, the full denoiser-classifier chain retains about 41% of the held-out signal traces, compared with 27% for the classifier acting on the raw waveform and about 2% for the peak-envelope reference. The fixed-point firmware is synthesised, placed, and routed on representative field-programmable gate array targets, where it achieves timing closure with microsecond-scale latency and compact arithmetic-resource usage. These results establish hybrid neural denoising as a practical FPGA-compatible route toward radio-only triggering of weak and inclined air-shower signals in noisy environments.

astro-ph.IM↗

arXiv2026

Hardware-efficient neural networks for FPGA-based radio triggering of extensive air showers

We present a hardware-efficient hybrid trigger for FPGA-based radio detection of extensive air showers. The hybrid design consists of a lightweight denoiser that cleans raw ADC traces and a compact classifier that operates on the denoised output, enabling robust near-threshold pulse detection in high-interference environments. Both neural networks are trained quantization-aware. Signals are generated from detector-folded CoREAS/CORSIKA simulations and embedded into measured noise to form a realistic benchmark. The trigger reaches an AUC of 0.992 while fitting comfortably within the resource budget of a Zynq-7000 Z-7020, with microsecond-scale latency and sub-watt power consumption. RTL validation confirms agreement between the fixed-point hardware and the quantized software model, demonstrating that neural denoising combined with classification provides reliable, low-cost radio triggering in noisy environments.

astro-ph.IM↗

arXiv2026

OTTER - Two Transistor - One RRAM Architecture for Reliable In-Memory-Computing in 28 nm CMOS Technology

This work presents OTTER, a 28 nm CMOS platform co-integrated with TaOx-based valence-change mechanism (VCM) RRAM, demonstrating a two-transistor-one-memristive-device (2T1R) architecture for reliable in-memory computing. The 2T1R cell combines a low-drive-current (LD) transistor and a high-drive-current (HD) transistor in parallel, providing dedicated bias paths for SET programming and RESET operation, respectively. Through systematic experimental and simulated comparison of various transistor-pairing configurations using the physical compact model JART VCM Rth, design guidelines for transistor sizing are derived, establishing the minimum RESET transistor W/L required for complete RESET as a function of the SET current compliance. The 2T1R cell is further characterized under pulse-based programming, demonstrating multilevel analog conductance tuning with narrow, well separated conductance states across six programmable levels. An analog content-addressable memory (aCAM) design based on the same 2T1R cell is additionally analyzed at the circuit level, evaluating trade-offs between top- and bottom-connected RRAM comparator configurations. A hardware implementation of compute-in-memory (CIM) multiply-and-accumulate (MAC) operations is further demonstrated on a 15 x 15 2T1R crossbar array.

cs.ET↗

arXiv2026

A dual-polarization whitened-template trigger for real-time radio detection of extensive air showers

Autonomous radio stations require a first-stage trigger that rejects measured background while preserving weak extensive-air-shower pulses under tight hardware constraints. We present a dual-polarization trigger based on a 16-sample whitened pulse template evaluated continuously on the orthogonal north-south and east-west channels of an Auger Engineering Radio Array station. The template is derived from detector-folded air-shower pulses and whitened using the covariance of measured background. Responses from both polarizations are combined within a fixed timing radius and compared with a calibrated threshold. On an independent test set, the trigger reaches an efficiency of 0.97, with a 95 percent confidence interval of 0.96 to 0.98, at a frame-equivalent candidate rate of 3.39 kHz. At the same operating point, an unwhitened dual-polarization template reaches 0.41 efficiency and an amplitude trigger reaches 0.16. Efficiency remains at least 0.94 in every populated signal-to-noise bin. Replay of 159.29 ms of continuous measured background yields a score-cluster rate of 6.64 kHz, below the 71.4 kHz capacity of the downstream module. The FPGA implementation accepts one dual-polarization sample per clock, closes timing at 200 MHz, and uses 2377 lookup tables, 5330 registers, and 32 digital signal-processing blocks. Register-transfer-level simulation agrees bit for bit with the reference implementation for 400 traces. These results show that background covariance, pulse morphology, and dual-polarization consistency can be combined in a compact real-time radio trigger.

astro-ph.IM↗

arXiv2026

Quantization Effects of Artificial Neural Networks for Embedded Edge-Computing Applications

This paper examines the use of Quantized Neural Networks (QNNs) for two resource-constrained scientific applications: automated calibration of semi- conductor quantum bits (qubits) and scientific particle detectors. We evaluate the trade-offs between Post-Training Quantization (PTQ), Quantization-Aware Train- ing (QAT), and ultra-low-bit Binary Neural Networks (BNNs) with respect to la- tency and resource usage. Our results demonstrate that PTQ and QAT are easily implementable solutions achieving a four-fold reduction in memory usage for U- shaped CNN (U-Net) architectures, whereas BNNs are better suitable for use cases with challenging latency requirements. For the training of non-differentiable custom BNNs , we propose a novel, hardware-constrained learning approach using Genetic Algorithms (GAs). We showcase a Look-Up Table (LUT)-based BNN architecture suitable for direct conversion to Very High-Speed Integrated Circuit Hardware De- scription Language (VHDL) via the HCL4BNN framework. This method achieves nanosecond-scale inference latencies at 10 ns to 15 ns without requiring specialized Digital Signal Processor (DSP) or Block RAM (BRAM) resources.

cs.NE↗

arXiv2026

Valley-Aware Optimal Control of Spin Shuttling Using Cryogenic Integrated Electronics

Electron shuttling is emerging as a key mechanism for enabling long-range coupling in scalable spin-qubit architectures. Bringing shuttling waveform generation into the cryostat can improve scalability, but imposes strict area and power constraints on the control electronics. Concurrently, shuttling in Si/SiGe is further limited by a spatially varying valley splitting that induces spin--valley mixing and degrades coherence. Here, we make three contributions that address these limitations jointly: (i) an end-to-end co-simulation framework that combines disorder-informed valley maps with transistor-level cryogenic circuit simulations including electronic noise; (ii) a fully integrated cryogenic shuttling-signal generator tailored to velocity modulation, enabling period-wise waveform shaping through discrete circuit settings stored in on-chip memory; and (iii) a noise-aware optimization procedure that tunes only these implementable circuit controls, using one of four discrete resistor settings per period, to generate high-fidelity shuttling sequences. Across simulated valley and noise realizations in our co-simulation framework, the optimized velocity-modulation waveforms improve transport performance, achieving an average shuttling fidelity of $99.99 \pm 0.007\%$ at $v_{\mathrm{avg}} = 20~\mathrm{m\,s^{-1}}$ over a distance of $10~μ\mathrm{m}$, while maintaining active analog power consumption in the tens of $μ\mathrm{W}$ during shuttling. This validates on-chip storage and replay of optimized control settings as a practical strategy to mitigate valley disorder in scalable shuttling architectures.

quant-ph↗

arXiv2025

Automated Charge Transition Detection in Quantum Dot Charge Stability Diagrams

Gate-defined semiconductor quantum dots require an appropriate number of electrons to function as qubits. The number of electrons is usually tuned by analyzing charge stability diagrams, in which charge transitions manifest as edges. Therefore, to fully automate qubit tuning, it is necessary to recognize these edges automatically and reliably. This paper investigates possible detection methods, describes their training with simulated data from the SimCATS framework, and performs a quantitative comparison with a future hardware implementation in mind. Furthermore, we investigated the quality of the optimized approaches on experimentally measured data from a GaAs and a SiGe qubit sample.

cond-mat.mes-hall↗

arXiv2025

On Noise-Sensitive Automatic Tuning of Gate-Defined Sensor Dots

In gate-defined quantum dot systems, the conductance change of electrostatically coupled sensor dots allows the observation of the quantum dots' charge and spin states. Therefore, the sensor dot must be optimally sensitive to changes in its electrostatic environment. A series of conductance measurements varying the two sensor-dot-forming barrier gate voltages serve to tune the dot into a corresponding operating regime. In this paper, we analyze the noise characteristics of the measured data and define a criterion to identify continuous regions with a sufficient signal-gradient-to-noise ratio. Hence, accurate noise estimation is required when identifying the optimal operating regime. Therefore, we evaluate several existing noise estimators, modify them for 1D data, optimize their parameters, and analyze their quality based on simulated data. The estimator of Chen et al. turns out to be best suited for our application concerning minimally scattering results. Furthermore, using this estimator in an algorithm for flank-of-interest classification in measured data shows the relevance and applicability of our approach.

cond-mat.mes-hall↗

arXiv2025

Simulation of Charge Stability Diagrams for Automated Tuning Solutions (SimCATS)

Quantum dots must be tuned precisely to provide a suitable basis for quantum computation. A scalable platform for quantum computing can only be achieved by fully automating the tuning process. One crucial step is to trap the appropriate number of electrons in the quantum dots, typically accomplished by analyzing charge stability diagrams (CSDs). Training and testing automation algorithms require large amounts of data, which can be either measured and manually labeled in an experiment or simulated. This article introduces a new approach to the realistic simulation of such measurements. Our flexible framework enables the simulation of ideal CSD data complemented with appropriate sensor responses and distortions. We suggest using this simulation to benchmark published algorithms. Also, we encourage the extension by custom models and parameter sets to drive the development of robust, technology-independent algorithms. Code is available at https://github.com/f-hader/SimCATS.

cond-mat.mes-hall↗

arXiv2025

2T1R Regulated Memristor Conductance Control Array Architecture for Neuromorphic Computing using 28nm CMOS Technology

Memristors are promising devices for scalable and low power, in-memory computing to improve the energy efficiency of a rising computational demand. The crossbar array architecture with memristors is used for vector matrix multiplication (VMM) and acts as kernels in neuromorphic computing. The analog conductance control in a memristor is achieved by applying voltage or current through it. A basic 1T1R array is suitable to avoid sneak path issues but suffer from wire resistances, which affects the read and write procedures. A conductance control scheme with a regulated voltage source will improve the architecture and reduce the possible potential divider effects. A change in conductance is also possible with the provision of a regulated current source and measuring the voltage across the memristors. A regulated 2T1R memristor conductance control architecture is proposed in this work, which avoids the potential divider effect and virtual ground scenario in a regular crossbar scheme, as well as conductance control by passing a regulated current through memristors. The sneak path current is not allowed to pass by the provision of ground potential to both terminals of memristors.

cs.ET↗

arXiv2025

Concept of a System-on-Chip Research Platform Benchmarking Interaction of Memristor-based Bio-inspired Computing Paradigms

A system architecture is suggested for a System on Chip that will combine several different memristor-based, bio-inspired computation arrays with inter- and intra-chip communication. It will serve as a benchmark system for future developments. The architecture takes the special requirements into account which are caused by the memristor co-integration on commercial CMOS structures in a post processing step of the chip. The interface considers the necessary data bandwidth to monitor the internal Network on Chip at speed and provides enough flexibility to give different measurement options.

cs.ET↗

arXiv2024

Design Space Exploration for Particle Detector Read-out Implementations in Matlab and Simulink on the Example of the SHiP SBT

On a very fundamental level, particle detectors share similar requirements for their read-out chain. This is reflected in the way that typical read-out solutions are developed, where a previous design is taken and modified to fit some changes in requirements. One of the two common approaches is the current-based read-out, where the waveform of the sensor output is sampled in order to later extract information from there. This approach is used in many detector applications using scintillation based detectors, including PET. With this contribution, we will introduce how we use Matlab in order to simulate the read-out electronics of particle detectors. We developed this simulation approach as a base for our ongoing development of software-defined read-out ASICs that cover the requirements of a variety of particle detector types. Simulink was chosen as a base for our developments as it allows simulation of mixed-signal systems and comes with built-in toolkits to aid in developments of such systems. With our approach, we want to take a new look at how we approach designing such a read-out, with a focus on digital signal processing close to the sensor, making use of known signal characteristics and modern methods of communications engineering. We are taking into account the time profile of an event, the bandwidth-limiting properties of the sensor and attached electronics, digitization stages and finally the parameterization of approaches for digital processing of the signal. We will show how we are applying the design approach to the development of a read-out for the proposed SHiP SBT detector, which is a scintillation based detector relying on SiPMs sensors, using this as an example for our modelling approach and show preliminary results.

physics.ins-det↗

arXiv2022

Potential for a precision measurement of solar $pp$ neutrinos in the Serappis Experiment

The Serappis (SEarch for RAre PP-neutrinos In Scintillator) project aims at a precision measurement of the flux of solar $pp$ neutrinos on the few-percent level. Such a measurement will be a relevant contribution to the study of solar neutrino oscillation parameters and a sensitive test of the solar luminosity constraint. The concept of Serappis relies on a small organic liquid scintillator detector ($\sim$20 m$^3$) with excellent energy resolution ($\sim$2.5 % at 1 MeV), low internal background and sufficient shielding from surrounding radioactivity. This can be achieved by a minor upgrade of the OSIRIS facility at the site of the JUNO neutrino experiment in southern China. To go substantially beyond current accuracy levels for the $pp$ flux, an organic scintillator with ultra-low $^{14}$C levels (below $10^{-18}$) is required. The existing OSIRIS detector and JUNO infrastructure will be instrumental in identifying suitable scintillator materials, offering a unique chance for a low-budget high-precision measurement of a fundamental property of our Sun that will be otherwise hard to access.

physics.ins-det↗

arXiv2020

Minimal Chimera States in Phase-Lag Coupled Mechanical Oscillators

We obtain experimental chimera states in the minimal network of three identical mechanical oscillators (metronomes), by introducing phase-lagged all-to-all coupling. For this, we have developed a real-time model-in-the-loop coupling mechanism that allows for flexible and online change of coupling topology, strength and phase-lag. The chimera states manifest themselves as a mismatch of average frequency between two synchronous and one desynchronized oscillator. We find this kind of striking chimeric behavior is robust in a wide parameter region. At other parameters, however, chimera state can lose stability and the system behavior manifests itself as a heteroclinic switching between three saddle-type chimeras. Our experimental observations are in a qualitative agreement with the model simulation.

nlin.AO↗

arXiv2019

Control Electronics For Semiconductor Spin Qubits

Future universal quantum computers solving problems of practical relevance are expected to require at least $10^6$ qubits, which is a massive scale-up from the present numbers of less than 50 qubits operated together. Out of the different types of qubits, solid state qubits are considered to be viable candidates for this scale-up, but interfacing to and controlling such a large number of qubits is a complex challenge that has not been solved yet. One possibility to address this challenge is to use qubit control circuits located close to the qubits at cryogenic temperatures. In this work we evaluate the feasibility of this idea, taking as a reference the physical requirements of a two-electron spin qubit and the specifications of a standard 65 nm complementary metal-oxide-semiconductor (CMOS) process. Using principles and flows from electrical systems engineering we provide realistic estimates of the footprint and of the power consumption of a complete control-circuit architecture. Our results show that with further research it is possible to provide scalable electrical control in the vicinity of the qubit, with our concept.

quant-ph↗