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Suman Das

Publications and source records attributed to Suman Das.

40 records · Page 3Linked to original sources
arXiv2018

A Lattice Model of Charge-Pattern-Dependent Polyampholyte Phase Separation

In view of recent intense experimental and theoretical interests in the biophysics of liquid-liquid phase separation (LLPS) of intrinsically disordered proteins (IDPs), heteropolymer models with chain molecules configured as self-avoiding walks on the simple cubic lattice are constructed to study how phase behaviors depend on the sequence of monomers along the chains. To address pertinent general principles, we focus primarily on two fully charged 50-monomer sequences with significantly different charge patterns. Each monomer in our models occupies a single lattice site and all monomers interact via a screened pairwise Coulomb potential. Phase diagrams are obtained by extensive Monte Carlo sampling performed at multiple temperatures on ensembles of 300 chains in boxes of sizes ranging from $52\times 52\times 52$ to $246\times 246\times 246$ to simulate a large number of different systems with the overall polymer volume fraction $ϕ$ in each system varying from $0.001$ to $0.1$. Phase separation in the model systems is characterized by the emergence of a large cluster connected by inter-monomer nearest-neighbor lattice contacts and by large fluctuations in local polymer density. The simulated critical temperatures, $T_{\rm cr}$, of phase separation for the two sequences differ significantly, whereby the sequence with a more "blocky" charge pattern exhibits a substantially higher propensity to phase separate. The trend is consistent with our sequence-specific random-phase-approximation (RPA) polymer theory, but the variation of the simulated $T_{\rm cr}$ with a previously proposed "sequence charge decoration" pattern parameter is milder than that predicted by RPA. Ramifications of our findings for the development of analytical theory and simulation protocols of IDP LLPS are discussed.

q-bio.BM↗
arXiv2014

A New Advanced User Authentication and Confidentiality Security Service

Network & internet security is the burning question of today's world and they are deeply related to each other for secure successful data transmission. Network security approach is totally based on the concept of network security services. In this paper, a new system of network security service is implemented which is more secure than conventional network security services. This technique is mainly deals with two essential network security services, one is user authentication and other is data confidentiality. For user authentication this paper introduces Graphical Username & Voice Password approaches which provides better security than conventional username & password authentication process. In data confidentiality section this paper introduces two layer private key for both message encryption & decryption which is mainly applicable on 8 bit plain text data. This paper also provides the hints of introducing other two network security services (integrity and non-repudiation) as a future work.

cs.CR↗
arXiv2012

A simple 1-byte 1-clock RC4 design and its efficient implementation in FPGA coprocessor for secured ethernet communication

In the field of cryptography till date the 1-byte in 1-clock is the best known RC4 hardware design [1], while the 1-byte in 3clocks is the best known implementation [2,3]. The design algorithm in [1] considers two consecutive bytes together and processes them in 2 clocks. The design of 1-byte in 3-clocks is too much modular and clock hungry. In this paper considering the RC4 algorithm, as it is, a simpler RC4 hardware design providing higher throughput is proposed in which 1-byte is processed in 1-clock. In the design two sequential tasks are executed as two independent events during rising and falling edges of the same clock and the swapping is directly executed using a MUX-DEMUX combination. The power consumed in behavioral and structural designs of RC4 are estimated and a power optimization technique is proposed. The NIST statistical test suite is run on RC4 key streams in order to know its randomness property. The encryption and decryption designs are respectively embedded on two FPGA boards with RC4 in a custom coprocessor followed by Ethernet communication.

cs.AR↗