arXiv subjects

Sumeet K. Gupta

Publications and source records attributed to Sumeet K. Gupta.

16 recordsLinked to original sources

arXiv2026

Zr Concentration-Dependent Sub-Lattice Phase-Field Model of Hf1-xZrxO2: Analysis of Phase Composition and Polarization Switching

We develop a sub-lattice phase-field model of Hf1-xZrxO2 incorporating zirconium (Zr) concentration (x)-dependence. Our framework expands the time-dependent Ginzburg-Landau (TDGL) equation to the sub-lattice level and incorporates x-dependent interaction parameters and gradient coefficients. Our experimentally calibrated model captures the evolution of charge-voltage (Q-V) characteristics for x ranging from 0.5 to 1.0. The sub-lattice formulation explains the thermodynamic preference and kinetic transition barriers of competing orthorhombic phase (o-phase) and tetragonal phase (t-phase), while the phase-field framework enables spatially resolved analysis of polarization (P) and electric-field (E-field) profiles, allowing multi-domain (MD) polarization and mixed-phase states to emerge naturally. Our model reproduces the experimentally observed ferroelectric (FE)-to-anti-ferroelectric (AFE) transition as x increases from 0.5 to 1.0. At low Zr concentration (x = 0.5-0.6), the o-phase dominates, yielding distinct FE behavior. At high concentration (x = 0.9-1.0), the t-phase is stabilized, leading to AFE transitions. A key finding of our work is the unique behavior at intermediate Zr concentrations (x = 0.7-0.8). Here, the o- and t-phase energies are comparable, making the system strongly influenced by local variations in the electric field (E-field), which arise from stray fields near the domain walls. This non-uniform field distribution results in a mixed-phase composition and spatially staggered polarization reversal, which manifests as a more gradual Q-V evolution compared to other values of x. By linking energy landscapes to spatial field effects, the model provides insights into the FE-to-AFE crossover in Hf1-xZrxO2.

cond-mat.mtrl-sci↗

arXiv2026

Negative-Voltage-Enabled Energy Efficient Nonvolatile Memories And In-Memory Computing Based On 2D Piezoelectric Transistors

Piezoelectric FET (PeFET) is a promising non-volatile-memory (NVM) device that integrates a piezoelectric (PE)/ferroelectric (FE) capacitor with a 2D transistor. It uses the polarization of the FE capacitor for bit-storage and strain-induced bandgap change of the 2D channel during read. Previous PeFET-based NVM designs have shown immense promise in achieving high density and energy-efficiency compared to SRAM. However, a key limitation of these designs is that they must trade-off integration density to enhance energy-efficiency or augment the memory functionality with in-memory computing (IMC). In this work, we show that the unique structure of the PeFET presents an appealing opportunity to counter these limitations, thereby simultaneously achieving high density, high energy-efficiency, and IMC-compatibility. First, we highlight the key reasons for the limited energy-efficiency of the previous PeFET designs. Based on these insights, we propose two flavors of PeFET memories that utilize negative voltage (NeVo) to reduce the major energy-consuming components significantly. Compared to 6T-SRAM (prior PeFET-based NVMs), the proposed designs achieve substantial reductions in energy, lowering read energy to 0.08x(0.03x) and write energy to 0.19x(0.53x), respectively. We then leverage these cells to implement IMC primitives, such as addition, subtraction, and multiply-and-accumulate (MAC), achieving 0.03x the energy consumption of prior PeFET-based designs.

cs.ET↗

arXiv2024

SiTe CiM: Signed Ternary Computing-in-Memory for Ultra-Low Precision Deep Neural Networks

Ternary Deep Neural Networks (DNN) have shown a large potential for highly energy-constrained systems by virtue of their low power operation (due to ultra-low precision) with only a mild degradation in accuracy. To enable an energy-efficient hardware substrate for such systems, we propose a compute-enabled memory design, referred to as SiTe-CiM, which features computing-in-memory (CiM) of dot products between signed ternary (SiTe) inputs and weights. SiTe CiM is based on cross-coupling of two bit cells to enable CiM of dot products in the signed ternary regime. We explore SiTe CiM with 8T-SRAM, 3T-embedded DRAM (3T-eDRAM) and 3T-ferroelectric metal FET (FEMFET) memories. We propose two flavors of this technique, namely SiTe CiM I/II. In SiTe CiM I, we employ two additional transistors per cell for cross-coupling, achieving fast CiM operations, albeit incurring an area overhead ranging from 18% to 34% (compared to standard ternary memories). In SiTe CiM II, four extra transistors are utilized for every 16 cells in a column, thereby incurring only 6% area cost (but leading to slower CiM than SiTe CiM I). Based on the array analysis, our designs achieve up to 88% lower CiM latency and 78% CiM energy savings across various technologies considered, as compared to their respective near-memory computing counterparts. Further, we perform system level analysis by incorporating SiTe CiM I/II arrays in a ternary DNN accelerator and show up to 7X throughput boost and up to 2.5X energy reduction compared to the near-memory ternary DNN accelerators.

cs.AR↗

arXiv2024

Comparative Evaluation of Memory Technologies for Synaptic Crossbar Arrays -- Part I: Robustness-driven Device-Circuit Co-Design and System Implications

In-memory computing (IMC) utilizing synaptic crossbar arrays is promising for energy-efficient deep neural network (DNN) accelerators. Various technologies (CMOS and post-CMOS) have been explored as synaptic device candidates, each with its own pros and cons. In this work, we perform a design space exploration and comparative evaluation of four technologies viz. 8T SRAMs, ferroelectric transistors (FeFETs), resistive RAMs (ReRAMs) and spin-orbit torque magnetic RAMs (SOT-MRAMs) in the context of IMC robustness and DNN accuracy. For a fair comparison, we carefully optimize each technology specifically for synaptic crossbar design accounting for device and circuit non-idealities. By integrating different technologies into a cross-layer simulation flow based on physical models of synaptic devices and interconnects, we present insights into various device-circuit interactions. Based on the optimized designs, we obtain inference results for ResNet-20 on CIFAR-10 dataset. Among the four technologies, we show that FeFETs-based DNNs achieve the highest accuracy (followed closely by ReRAMs) and the largest resilience to process variations due to the compactness and high ON/OFF current ratio of FeFET bit-cells. In Part II of this paper, we expand the technology evaluation considering various device-circuit design knobs used for crossbar arrays.

cs.ET↗

arXiv2024

Comparative Evaluation of Memory Technologies for Synaptic Crossbar Arrays- Part 2: Design Knobs and DNN Accuracy Trends

Crossbar memory arrays have been touted as the workhorse of in-memory computing (IMC)-based acceleration of Deep Neural Networks (DNNs), but the associated hardware non-idealities limit their efficacy. To address this, cross-layer design solutions that reduce the impact of hardware non-idealities on DNN accuracy are needed. In Part 1 of this paper, we established the co-optimization strategies for various memory technologies and their crossbar arrays, and conducted a comparative technology evaluation in the context of IMC robustness. In this part, we analyze various design knobs such as array size and bit-slice (number of bits per device) and their impact on the performance of 8T SRAM, ferroelectric transistor (FeFET), Resistive RAM (ReRAM) and spin-orbit-torque magnetic RAM (SOT-MRAM) in the context of inference accuracy at 7nm technology node. Further, we study the effect of circuit design solutions such as Partial Wordline Activation (PWA) and custom ADC reference levels that reduce the hardware non-idealities and comparatively analyze the response of each technology to such accuracy enhancing techniques. Our results on ResNet-20 (with CIFAR-10) show that PWA increases accuracy by up to 32.56% while custom ADC reference levels yield up to 31.62% accuracy enhancement. We observe that compared to the other technologies, FeFET, by virtue of its small layout height and high distinguishability of its memory states, is best suited for large arrays. For higher bit-slices and a more complex dataset (ResNet-50 with Cifar-100) we found that ReRAM matches the performance of FeFET.

cs.ET↗

arXiv2024

Small Signal Capacitance in Ferroelectric HZO: Mechanisms and Physical Insights

This study presents a theoretical investigation of the physical mechanisms governing small signal capacitance in ferroelectrics, focusing on Hafnium Zirconium Oxide. Utilizing a time-dependent Ginzburg Landau formalism-based 2D multi-grain phase-field simulation framework, we simulate the capacitance of metal-ferroelectric-insulator-metal (MFIM) capacitors. Our simulation methodology closely mirrors the experimental procedures for measuring ferroelectric small signal capacitance, and the outcomes replicate the characteristic butterfly capacitance-voltage behavior. We delve into the components of the ferroelectric capacitance associated with the dielectric response and polarization switching, discussing the primary physical mechanisms - domain bulk response and domain wall response - contributing to the butterfly characteristics. We explore their interplay and relative contributions to the capacitance and correlate them to the polarization domain characteristics. Additionally, we investigate the impact of increasing domain density with ferroelectric thickness scaling, demonstrating an enhancement in the polarization capacitance component (in addition to the dielectric component). We further analyze the relative contributions of the domain bulk and domain wall responses across different ferroelectric thicknesses. Lastly, we establish the relation of polarization capacitance components to the capacitive memory window (for memory applications) and reveal a non-monotonic dependence of the maximum memory window on HZO thickness.

cond-mat.mtrl-sci↗

arXiv2023

Direction-Dependent Lateral Domain Walls in Ferroelectric Hafnium Zirconium Oxide and their Gradient Energy Coefficients: A First Principles Study

To understand and harness the physical mechanisms of ferroelectric Hafnium Zirconium Oxide (HZO)-based devices, there is a need for clear understanding of domain interactions, their dynamics, negative capacitance effects, and other multi-domain characteristics. These crucial attributes depend on the coupling between neighboring domains quantified by the gradient energy coefficient (g). Furthermore, HZO has unique orientation-dependent lateral multidomain configurations. To develop an in-depth understanding of multi-domain effects, there is a need for thorough analysis of g. In this work, the energetics of multidomain configurations and domain growth mechanism corresponding to lateral domain walls of HZO are analyzed and gradient energy coefficients are quantified using first-principles Density Functional Theory calculations. These results indicate that one lateral direction exhibits the following characteristics: i) DW is ultra-sharp and domain growth occurs unit-cell-by-unit-cell, ii) the value of g is negative and in the order of $10^{-12} Vm^{3}C^{-1}$, and iii) g reduces (increases) with compressive (tensile) strain. In contrast, in the other lateral direction, the following attributes are observed: i) DW is gradual and domain growth occurs in quanta of half-unit-cell, ii) g is positive and in the order of $10^{-10} Vm^{3}C^{-1}$, and iii) g increases (reduces) with compressive (tensile) strain.

cond-mat.mtrl-sci↗

arXiv2023

Head-to-Head and Tail-to-Tail Domain Wall in Hafnium Zirconium Oxide: A First Principles Analysis of Domain Wall Formation and Energetics

180° domains walls (DWs) of Head-to-Head/Tail-to-Tail (H-H/T-T) type in ferroelectric (FE) materials are of immense interest for a comprehensive understanding of the FE attributes as well as harnessing them for new applications. Our first principles calculation suggests that such DW formation in Hafnium Zirconium Oxide (HZO) based FEs depends on the unique attributes of the HZO unit cell, such as polar-spacer segmentation. Cross pattern of the polar and spacer segments in two neighboring domains along the polarization direction (where polar segment of one domain aligns with the spacer segment of another) boosts the stability of such DWs. We further show that low density of oxygen vacancies at the metal-HZO interface and high work function of metal electrodes are conducive for T-T DW formation. On the other hand, high density of oxygen vacancy and low work function of metal electrode favor H-H DW formation. Polarization bound charges at the DW get screened when band bending from depolarization field accumulates holes (electrons) in T-T (H-H) DW. For a comprehensive understanding, we also investigate their FE nature and domain growth mechanism. Our analysis suggests that a minimum thickness criterion of domains has to be satisfied for the stability of H-H/T-T DW and switching of the domains through such DW formation.

cond-mat.mtrl-sci↗

arXiv2023

Phase-field Simulations of Polarization Variations in Polycrystalline Hf0.5Zr0.5O2 based MFIM: Voltage-Dependence and Dynamics

In this work, we investigate the device-to-device variations in remanent polarization of Hafnium-Zirconium-Oxide based Metal-Ferroelectric-Insulator-Metal (MFIM) stacks. We consider the effects of polycrystallinity in conjunction with multi-domain effects in HZO to understand the dependencies of variations on static and dynamic voltage stimuli using our 3D dynamic multi-grain phase-field simulation framework. We examine the trends in variations due to various design factors - set voltage, pulse amplitude and pulse width and correlate them to the dynamics of polarization switching and the underlying mechanisms. According to our analysis, variations exhibit a non-monotonic dependence on set voltage due to the interplay between voltage-dependent switching mechanisms and the polycrystalline structure. We further report that towards the higher end of the set voltages, collapsing of oppositely polarized domains can lead to increase in variations. We also show that ferroelectric thickness scaling lowers the device-to-device variations. In addition, considering the dynamics of polarization switching, we signify the key role of voltage and temporal dependence of domain nucleation in dictating the trends in variations. Finally, we show that to reach a target mean polarization, using a pulse with lower amplitude for longer duration results in lower variations compared to higher amplitude pulse for a shorter duration.

physics.comp-ph↗

arXiv2022

Piezoelectric Strain FET (PeFET) based Non-Volatile Memories

We propose non-volatile memory (NVM) designs based on Piezoelectric Strain FET (PeFET) utilizing a piezoelectric/ferroelectric (PE/FE such as PZT) coupled with 2D Transition Metal Dichalcogenide (2D-TMD such as MoS2) transistor. The proposed NVMs store bit information in the form of polarization (P) of the FE/PE, use electric-field driven P-switching for write and employ piezoelectricity induced dynamic bandgap modulation of 2D-TMD channel for bit sensing. We analyze PeFET with COMSOL based 3D modeling showing that the circuit-driven optimization of PeFET geometry is essential to achieve effective hammer-and-nail effect and adequate bandgap modulation for NVM read. Our results show that distinguishability of binary states to up to 11X is achieved in PeFETs.We propose various flavors of PeFET NVMs, namely (a) high density (HD) NVM featuring a compact access-transistor-less bit-cell, (b) 1T-1PeFET NVM with segmented architecture, targeted for optimized write energy and latency and (c) cross-coupled (CC) NVM offering a trade-off between area and latency.PeFET NVMs offer up to 7X smaller cell area, 66% lower write energy, 87% lower read energy and 44% faster read compared to 2D-FET SRAM. This comes at the cost of high write latency in PeFET NVMs, which can be minimized by virtue of optimized PE geometry.

cs.ET↗

arXiv2022

STeP-CiM: Strain-enabled Ternary Precision Computation-in-Memory based on Non-Volatile 2D Piezoelectric Transistors

We propose 2D Piezoelectric FET (PeFET) based compute-enabled non-volatile memory for ternary deep neural networks (DNNs). PeFETs consist of a material with ferroelectric and piezoelectric properties coupled with Transition Metal Dichalcogenide channel. We utilize (a) ferroelectricity to store binary bits (0/1) in the form of polarization (-P/+P) and (b) polarization dependent piezoelectricity to read the stored state by means of strain-induced bandgap change in Transition Metal Dichalcogenide channel. The unique read mechanism of PeFETs enables us to expand the traditional association of +P (-P) with low (high) resistance states to their dual high (low) resistance depending on read voltage. Specifically, we demonstrate that +P (-P) stored in PeFETs can be dynamically configured in (a) a low (high) resistance state for positive read voltages and (b) their dual high (low) resistance states for negative read voltages, without afflicting a read disturb. Such a feature, which we name as Polarization Preserved Piezoelectric Effect Reversal with Dual Voltage Polarity (PiER), is unique to PeFETs and has not been shown in hitherto explored memories. We leverage PiER to propose a Strain-enabled Ternary Precision Computation-in-Memory (STeP-CiM) cell with capabilities of computing the scalar product of the stored weight and input, both of which are represented with signed ternary precision. Further, using multi word-line assertion of STeP-CiM cells, we achieve massively parallel computation of dot products of signed ternary inputs and weights. Our array level analysis shows 91% lower delay and improvements of 15% and 91% in energy for in-memory multiply-and-accumulate operations compared to near-memory design approaches based on SRAM and PeFET respectively. STeP-CiM exhibits upto 8.91x improvement in performance and 6.07x average improvement in energy over SRAM/PeFET based near-memory design.

cs.ET↗

arXiv2022

ADRA: Extending Digital Computing-in-Memory with Asymmetric Dual-Row-Activation

Computing in-memory (CiM) has emerged as an attractive technique to mitigate the von-Neumann bottleneck. Current digital CiM approaches for in-memory operands are based on multi-wordline assertion for computing bit-wise Boolean functions and arithmetic functions such as addition. However, most of these techniques, due to the many-to-one mapping of input vectors to bitline voltages, are limited to CiM of commutative functions, leaving out an important class of computations such as subtraction. In this paper, we propose a CiM approach, which solves the mapping problem through an asymmetric wordline biasing scheme, enabling (a) simultaneous single-cycle memory read and CiM of primitive Boolean functions (b) computation of any Boolean function and (c) CiM of non-commutative functions such as subtraction and comparison. While the proposed technique is technology-agnostic, we show its utility for ferroelectric transistor (FeFET)-based non-volatile memory. Compared to the standard near-memory methods (which require two full memory accesses per operation), we show that our method can achieve a full scale two-operand digital CiM using just one memory access, leading to a 23.2% - 72.6% decrease in energy-delay product (EDP).

cs.AR↗

arXiv2021

Multi-domain Polarization Switching in Hf0.5Zr0.5O2-Dielectric Stack: The Role of Dielectric Thickness

We investigate the polarization switching mechanism in ferroelectric-dielectric (FE-DE) stacks and its dependence on the dielectric thickness (TDE). We fabricate HZO-Al2O3 (FE-DE) stack and experimentally demonstrate a decrease in remnant polarization and an increase in coercive voltage of the FE-DE stack with an increase in TDE. Using phase-field simulations, we show that an increase in TDE results in a larger number of reverse domains in the FE layer to suppress the depolarization field, which leads to a decrease in remanent polarization and an increase in coercive voltage. Further, the applied voltage-driven polarization switching suggests domain-nucleation dominant characteristics for low TDE, and domain-wall motion-induced behavior for higher TDE. In addition, we show that the hysteretic charge-voltage characteristics of the FE layer in the FE-DE stack exhibit a negative slope region due to the multi-domain polarization switching in the FE layer. Based on our analysis, the trends in charge-voltage characteristics of the FE-DE stack with respect to different TDE (which are out of the scope of single-domain models) can be described well with multi-domain polarization switching mechanisms.

physics.app-ph↗

arXiv2020

$α$-In$_2$Se$_3$ based Ferroelectric-Semiconductor Metal Junction for Non-Volatile Memories

In this work, we theoretically and experimentally investigate the working principle and non-volatile memory (NVM) functionality of 2D $α$-In$_2$Se$_3$ based ferroelectric-semiconductor-metal-junction (FeSMJ). First, we analyze the semiconducting and ferroelectric properties of $α$-In$_2$Se$_3$ van-der-Waals (vdW) stack via experimental characterization and first-principle simulations. Then, we develop a FeSMJ device simulation framework by self-consistently solving Landau-Ginzburg-Devonshire (LGD) equation, Poisson's equation, and charge-transport equations. Based on the extracted FeS parameters, our simulation results show good agreement with the experimental characteristics of our fabricated $α$-In$_2$Se$_3$ based FeSMJ. Our analysis suggests that the vdW gap between the metal and FeS plays a key role to provide FeS polarization-dependent modulation of Schottky barrier heights. Further, we show that the thickness scaling of FeS leads to a reduction in read/write voltage and an increase in distinguishability. Array-level analysis of FeSMJ NVM suggests a 5.47x increase in sense margin, 18.18x reduction in area and lower read-write power with respect to Fe insulator tunnel junction (FTJ).

physics.app-ph↗

arXiv2020

A Ferroelectric Semiconductor Field-Effect Transistor

Ferroelectric field-effect transistors employ a ferroelectric material as a gate insulator, the polarization state of which can be detected using the channel conductance of the device. As a result, the devices are of potential to use in non-volatile memory technology, but suffer from short retention times, which limits their wider application. Here we report a ferroelectric semiconductor field-effect transistor in which a two-dimensional ferroelectric semiconductor, indium selenide (α-In2Se3), is used as the channel material in the device. α-In2Se3 was chosen due to its appropriate bandgap, room temperature ferroelectricity, ability to maintain ferroelectricity down to a few atomic layers, and potential for large-area growth. A passivation method based on the atomic-layer deposition of aluminum oxide (Al2O3) was developed to protect and enhance the performance of the transistors. With 15-nm-thick hafnium oxide (HfO2) as a scaled gate dielectric, the resulting devices offer high performance with a large memory window, a high on/off ratio of over 108, a maximum on-current of 862 μA μm-1, and a low supply voltage.

physics.app-ph↗

arXiv2019

Room Temperature Electrocaloric Effect in Layered Ferroelectric CuInP2S6 for Solid State Refrigeration

A material with reversible temperature change capability under an external electric field, known as the electrocaloric effect (ECE), has long been considered as a promising solid-state cooling solution. However, electrocaloric (EC) performance of EC materials generally is not sufficiently high for real cooling applications. As a result, exploring EC materials with high performance is of great interest and importance. Here, we report on the ECE of ferroelectric materials with van der Waals layered structure (CuInP2S6 or CIPS in this work in particular). Over 60% polarization charge change is observed within a temperature change of only 10 K at Curie temperature. Large adiabatic temperature change (|ΔT|) of 3.3 K, isothermal entropy change (|ΔS|) of 5.8 J kg-1 K-1 at |ΔE|=142.0 kV cm-1 at 315 K (above and near room temperature) are achieved, with a large EC strength (|ΔT|/|ΔE|) of 29.5 mK cm kV-1. The ECE of CIPS is also investigated theoretically by numerical simulation and a further EC performance projection is provided.

cond-mat.mtrl-sci↗