arXiv subjects

Suraj S. Cheema

Publications and source records attributed to Suraj S. Cheema.

3 recordsLinked to original sources

arXiv2026

Probabilistic Sensing: Intelligence in Data Sampling

Extending the intelligence of sensors to the data-acquisition process - deciding whether to sample or not - can result in transformative energy-efficiency gains. However, making such a decision in a deterministic manner involves risk of losing information. Here we present a sensing paradigm that enables making such a decision in a probabilistic manner. The paradigm takes inspiration from the autonomous nervous system and employs a probabilistic neuron (p-neuron) driven by an analog feature extraction circuit. The response time of the system is on the order of microseconds, over-coming the sub-sampling-rate response time limit and enabling real-time intelligent autonomous activation of data-sampling. Validation experiments on active seismic survey data demonstrate lossless probabilistic data acquisition, with a normalized mean squared error of 0.41%, and 93% saving in the active operation time of the system and the number of generated samples.

cs.LG↗

arXiv2026

Configurable p-Neurons Using Modular p-Bits

Probabilistic bits (p-bits) have recently been employed in neural networks (NNs) as stochastic neurons with sigmoidal probabilistic activation functions. Nonetheless, there remain a wealth of other probabilistic activation functions that are yet to be explored. Here we re-engineer the p-bit by decoupling its stochastic signal path from its input data path, giving rise to a modular p-bit that enables the realization of probabilistic neurons (p-neurons) with a range of configurable probabilistic activation functions, including a probabilistic version of the widely used Logistic Sigmoid, Tanh and Rectified Linear Unit (ReLU) activation functions. We present spintronic (CMOS + sMTJ) designs that show wide and tunable probabilistic ranges of operation. Finally, we experimentally implement digital-CMOS versions on an FPGA, with stochastic unit sharing, and demonstrate an order of magnitude (10x) saving in required hardware resources compared to conventional digital p-bit implementations.

cs.ET↗

arXiv2020

One nanometer HfO$_2$-based ferroelectric tunnel junctions on silicon

In ferroelectric materials, spontaneous symmetry breaking leads to a switchable electric polarization, which offers significant promise for nonvolatile memories. In particular, ferroelectric tunnel junctions (FTJs) have emerged as a new resistive switching memory which exploit polarization-dependent tunnel current across a thin ferroelectric barrier. Here we demonstrate FTJs with CMOS-compatible Zr-doped HfO$_2$ (Zr:HfO$_2$) ferroelectric barriers of just 1 nm thickness, grown by atomic layer deposition on silicon. These 1 nm Zr:HfO$_2$ tunnel junctions exhibit large polarization-driven electroresistance (19000$\%$), the largest value reported for HfO$_2$-based FTJs. In addition, due to just a 1 nm ferroelectric barrier, these junctions provide large tunnel current (> 1 A/cm$^2$) at low read voltage, orders of magnitude larger than reported thicker HfO$_2$-based FTJs. Therefore, our proof-of-principle demonstration provides an approach to simultaneously overcome three major drawbacks of prototypical FTJs: a Si-compatible ultrathin ferroelectric, large electroresistance, and large read current for high-speed operation.

cond-mat.mtrl-sci↗