arXiv subjects

Suryanarayana Murthy Durbhakula

Publications and source records attributed to Suryanarayana Murthy Durbhakula.

5 recordsLinked to original sources

arXiv2020

ILP Aware Scheduling on Multithreaded Multi-core Processors

Multithreaded Multi-core processors are prevalent today and are used for solving some of the important problems in computing. Resource imbalance can negatively impact overall performance in such processors. Hence balanced resource utilization is important in such processors. Particularly, it is important to maximize utilization of available instruction-level-parallelism (ILP). In this paper I present an ILP aware operating system (OS) scheduling algorithm for Multithreaded Multi-core processors. By keeping track of available ILP in each thread and by balancing it with available ILP resources in the system the OS will come up with a new schedule of threads for the next quantum. This new schedule will potentially result in a more balanced resource-utilization and improve performance for the next quantum. This work can be extended by doing a detailed quantitative evaluation.

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arXiv2020

Near Linear OS Scheduling Optimization for Memory Intensive Workloads on Multi-socket Multi-core servers

Multi-socket multi-core servers are used for solving some of the important problems in computing. Remote DRAM accesses can impact performance of certain applications running on such servers. This paper presents a new near linear operating system (OS) scheduling algorithm to reduce the impact of such remote DRAM accesses. By keeping track of the number of local and remote DRAM accesses, using performance counters, for every thread and applying this algorithm, I come up with a new schedule of threads for the next quantum. This new schedule reduces remote DRAM accesses and improves overall performance. I also show that this algorithm is actually linear in the best case. As the algorithm is near-linear it is amenable for implementation in a real operating system.

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arXiv2020

Parallel Minimum Spanning Tree Algorithms and Evaluation

Minimum Spanning Tree (MST) is an important graph algorithm that has wide ranging applications in the areas of computer networks, VLSI routing, wireless communications among others. Today virtually every computer is built out of multi-core processors. Hence it is important to take advantage of such parallel computing power by parallelizing existing algorithms and applications. Most of the earlier work on parallelizing MST focused on algorithms for PRAM models. There are two limitations to such studies. First, PRAM models assume infinite memory bandwidth which is unrealistic. Second, PRAM model based algorithms require at least O(n) processors where n being total number of vertices. For large graphs this is infeasible. There are very few implementations which target real systems. In this paper I present and evaluate two new parallel MST algorithms that are a variant of Parallel Boruvka algorithms: i) First algorithm uses lock variables without spin-locks ii) Second algorithm uses only atomic compare-and-swap (CAS) primitive. I evaluated the performance of these algorithms on a six-core, 12-thread Intel system on various input graphs of sizes up to 1 million vertices. First algorithm showed a speedup of up to1.94 over an un-optimized sequential algorithm and a speedup of up to 1.4 over an optimized sequential algorithm. Second algorithm showed a speedup of up to 2.03 over an un-optimized sequential algorithm and a speedup of up to 1.403 over an optimized sequential algorithm. When second algorithm using CAS is compared with the first algorithm second algorithm is found to be up to 1.15 times better than the first algorithm at four threads.

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arXiv2019

Cache Optimization for Sharing Intensive Workloads on Multi-socket Multi-core servers

Major chip manufacturers have all introduced multicore microprocessors. Multi-socket systems built from these processors are used for running various server applications. Depending on the application, remote cache-to-cache transfers can severely impact the performance of such workloads. This paper presents a cache optimization that can cut down remote cache-to-cache transfers. By keeping track of remote cache lines loaded from remote caches into last-level-cache and by biasing the cache replacement policy towards such remote cache lines we can reduce the number of cache misses. This in turn results in improvement of overall performance. I present the design details in this paper. I do a qualitative comparison of various solutions to the problem of performance impact of remote cache-to-cache transfers. This work can be extended by doing a quantitative evaluation.

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arXiv2018

OS Scheduling Algorithms for Improving the Performance of Multithreaded Workloads

Major chip manufacturers have all introduced multicore microprocessors. Multi-socket systems built from these processors are used for running various server applications. However to the best of our knowledge current commercial operating systems are not optimized for multi-threaded workloads running on such servers. Cache-to-cache transfers and remote memory accesses impact the performance of such workloads. This paper presents a unified approach to optimizing OS scheduling algorithms for both cache-to-cache transfers and remote DRAM accesses that also takes cache affinity into account. By observing the patterns of local and remote cache-to-cache transfers as well as local and remote DRAM accesses for every thread in each scheduling quantum and applying different algorithms, we come up with a new schedule of threads for the next quantum taking cache affinity into account. This new schedule cuts down both remote cache-to-cache transfers and remote DRAM accesses for the next scheduling quantum and improves overall performance. We present two algorithms of varying complexity for optimizing cache-to-cache transfers. One of these is a new algorithm which is relatively simpler and performs better when combined with algorithms that optimize remote DRAM accesses. For optimizing remote DRAM accesses we present two algorithms. Though both algorithms differ in algorithmic complexity we find that for our workloads they perform equally well. We used three different synthetic workloads to evaluate these algorithms. We also performed sensitivity analysis with respect to varying remote cache-to-cache transfer latency and remote DRAM latency. We show that these algorithms can cut down overall latency by up to 16.79% depending on the algorithm used.

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