arXiv subjects

T. Hemperek

Publications and source records attributed to T. Hemperek.

16 recordsLinked to original sources

arXiv2026

Test-beam results from MiniCACTUS-v2: A depleted monolithic CMOS timing sensor prototype

MiniCACTUS-v2 is a monolithic sensor prototype designed in LF 150 nm CMOS process for time tagging of individual Minimum Ionizing Particles with an accuracy better than 100 ps. The sensing element is a deep n-well/p-substrate diode without internal amplification. To minimize detector capacitances, the analog front-ends and the discriminators for each pixel have been implemented outside the pixel, at the column level. After fabrication, the sensors have been thinned to 150 microns, 175 microns and 200 microns and then post-processed for backside biasing. The breakdown voltages measured on these sensors are higher than 500 V, ensuring the complete depletion of the charge collection volume. In this paper, we will focus on the time resolution measurements from a test-beam campaign conducted in July 2025 at SPS-CERN. During this period, several pixels from the 3 different sensor thicknesses have been tested at different bias voltages. The best time resolution measured is 48.88 ps on a 0.5 mm x 0.5 mm pixel from a 175 microns-thick sensor at 500 V, with nominal settings for the on-chip analog front-end and discriminator.

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arXiv2023

Characterization, Simulation and Test Beam Data Analysis of Stitched Passive CMOS Strip Sensors

In the passive CMOS Strips Project, strip sensors were designed at the University of Bonn and produced by LFoundry in 150 nm technology, with an additional backside processing from IZM Berlin. Up to five individual reticules were connected by stitching at the foundry in order to obtain the typical strip lengths required for the LHC Phase-II upgrade of ATLAS or CMS trackers. After dicing, sensors were tested in a probe station and characterised with a Sr90-source as well as laser-based edge- and top-TCT systems. Sensors were also simulated using Sentaurus TCAD. At last, detector modules were constructed from several sensors and thoroughly studied in two beam campaigns at DESY. All of these measurements were performed before and after irradiation. This contribution provides an overview of simulation results, summarises the laboratory measurements and in particular presents first test beam results for irradiated and unirradiated passive CMOS strip sensors. We are demonstrating that large area sensors with sufficient radiation hardness can be obtained by stitching during the CMOS process, and presenting our plans for the next submission in the framework of this project.

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arXiv2020

Radiation hard DMAPS pixel sensors in 150nm CMOS technology for operation at LHC

Monolithic Active Pixel Sensors (MAPS) have been developed since the late 1990s employing silicon substrate with a thin epitaxial layer in which deposited charge is collected by disordered diffusion rather than by drift in an electric field. As a consequence the signal is small and slow, and the radiation tolerance is below the requirements for LHC experiments by factors of 100 to 1000. We developed fully depleted (D)MAPS pixel sensors employing a 150 nm CMOS technology and using a high resistivity substrate as well as a high biasing voltage. The development has been carried out in three subsequent iterations, from prototypes to a large pixel matrix comprising a complete readout architecture suitable for LHC operation. Full CMOS electronics is embedded in large deep n-wells which at the same time serve as collection nodes (large electrode design). The devices have been intensively characterized before and after irradiation employing lab tests as well as particle beams. The devices can cope with particle rates seen by the innermost pixel detectors of the LHC pp-experiments or as seen by the outer pixel layers of the planned HL-LHC upgrade. They are radiation hard to particle fluences of at least $10^{15}~\mathrm{n_{eq}/cm^2}$ and total ionization doses of at least 50 Mrad.

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arXiv2020

Measurements of Single Event Upset in ATLAS IBL

Effects of Single Event Upsets (SEU) and Single Event Transients (SET) are studied in the FE-I4B chip of the innermost layer of the ATLAS pixel system. SEU/SET affect the FE-I4B Global Registers as well as the settings for the individual pixels, causing, among other things, occupancy losses, drops in the low voltage currents, noisy pixels, and silent pixels. Quantitative data analysis and simulations indicate that SET dominate over SEU on the load line of the memory. Operational issues and mitigation techniques are presented.

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arXiv2019

Mini-MALTA: Radiation hard pixel designs for small-electrode monolithic CMOS sensors for the High Luminosity LHC

Depleted Monolithic Active Pixel Sensor (DMAPS) prototypes developed in the TowerJazz 180 nm CMOS imaging process have been designed in the context of the ATLAS upgrade Phase-II at the HL-LHC. The pixel sensors are characterized by a small collection electrode (3 $μ$m) to minimize capacitance, a small pixel size ($36.4\times 36.4$ $μ$m), and are produced on high resistivity epitaxial p-type silicon. The design targets a radiation hardness of $1\times10^{15}$ 1 MeV n$_{eq}$/cm$^{2}$, compatible with the outermost layer of the ATLAS ITK Pixel detector. This paper presents the results from characterization in particle beam tests of the Mini-MALTA prototype that implements a mask change or an additional implant to address the inefficiencies on the pixel edges. Results show full efficiency after a dose of $1\times10^{15}$ 1 MeV n$_{eq}$/cm$^{2}$.

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arXiv2019

Compact, directional neutron detectors capable of high-resolution nuclear recoil imaging

We report on the design, production, and performance of compact 40-cm$^3$ Time Projection Chambers (TPCs) that detect fast neutrons by measuring the three-dimensional (3D) ionization distribution of nuclear recoils in $^4$He:CO$_2$ gas at atmospheric pressure. We use these detectors to characterize the fast-neutron flux inside the Belle II detector at the SuperKEKB electron-positron collider in Tsukuba, Japan, where the primary design constraint is a small form factor. We find that the TPCs meet or exceed all design specifications, and are capable of measuring the 3D surface shape and charge density profile of ionization clouds from nuclear recoils and charged tracks in exquisite detail. Scaled-up detectors based on the detection principle demonstrated here may be suitable for directional dark matter searches, measurements of coherent neutrino-nucleus scattering, and other experiments requiring precise detection of neutrons or nuclear recoils.

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arXiv2018

CMOS Monolithic Pixel Sensors based on the Column-Drain Architecture for the HL-LHC Upgrade

Depleted Monolithic Active Pixel Sensors (DMAPS) constitute a promising low cost alternative for the outer layers of the ATLAS experiment Inner Tracker (ITk). Realizations in modern, high resistivity CMOS technologies enhance their radiation tolerance by achieving substantial depletion of the sensing volume. Two DMAPS prototypes that use the same "column-drain" readout architecture and are based on different sensor implementation concepts named LF-Monopix and TJ-Monopix have been developed for the High Luminosity upgrade of the Large Hardon Collider (HL-LHC). LF-Monopix was fabricated in the LFoundry 150 nm technology and features pixel size of $50x250~μm^{2}$ and large collection electrode opted for high radiation tolerance. Detection efficiency up to 99\% has been measured after irradiation to $1\cdot10^{15}~n_{eq}/cm^{2}$. TJ-Monopix is a large scale $(1x2~cm^{2})$ prototype featuring pixels of $36x40~μm^{2}$ size. It was fabricated in a novel TowerJazz 180 nm modified process that enables full depletion of the sensitive layer, while employing a small collection electrode that is less sensitive to crosstalk. The resulting small sensor capacitance ($<=3~fF$) is exploited by a compact, low power front end optimized to meet the 25ns timing requirement. Measurement results demonstrate the sensor performance in terms of Equivalent Noise Charge (ENC) $\approx11e^{-}$, threshold $\approx300~e^-$, threshold dispersion $\approx30~e^-$ and total power consumption lower than $120~mW/cm^2$.

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arXiv2018

Characterization of a depleted monolithic pixel sensors in 150 nm CMOS technology for the ATLAS Inner Tracker upgrade

This work presents a depleted monolithic active pixel sensor (DMAPS) prototype manufactured in the LFoundry 150\,nm CMOS process. DMAPS exploit high voltage and/or high resistivity inclusion of modern CMOS technologies to achieve substantial depletion in the sensing volume. The described device, named LF-Monopix, was designed as a proof of concept of a fully monolithic sensor capable of operating in the environment of outer layers of the ATLAS Inner Tracker upgrade in 2025 for the High Luminosity Large Hadron Collider (HL-LHC). This type of devices has a lower production cost and lower material budget compared to presently used hybrid designs. In this work, the chip architecture will be described followed by the characterization of the different pre-amplifier and discriminator flavors with an external injection signal and an iron source (5.9\,keV x-rays).

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arXiv2018

Charge collection properties of irradiated depleted CMOS pixel test structures

Edge-TCT and charge collection measurements with passive test structures made in LFoundry 150 nm CMOS process on p-type substrate with initial resistivity of over 3 k$Ω$cm are presented. Measurements were made before and after irradiation with reactor neutrons up to 2$\cdot$10$^{15}$ n$_{\mathrm{eq}}$/cm$^2$. Two sets of devices were investigated: unthinned (700 $μ$m) with substrate biased through the implant on top and thinned (200 $μ$m) with processed and metallised back plane. Depleted depth was estimated with Edge-TCT and collected charge was measured with $^{90}$Sr source using an external amplifier with 25 ns shaping time. Depleted depth at given bias voltage decreased with increasing neutron fluence but it was still larger than 70 $μ$m at 250 V after the highest fluence. After irradiation much higher collected charge was measured with thinned detectors with processed back plane although the same depleted depth was observed with Edge-TCT. Most probable value of collected charge of over 5000 electrons was measured also after irradiation to 2$\cdot$10$^{15}$ n$_{\mathrm{eq}}$/cm$^2$. This is sufficient to ensure successful operation of these detectors at the outer layer of the pixel detector in the ATLAS experiment at the upgraded HL-LHC.

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arXiv2017

Charge collection properties in an irradiated pixel sensor built in a thick-film HV-SOI process

Investigation of HV-CMOS sensors for use as a tracking detector in the ATLAS experiment at the upgraded LHC (HL-LHC) has recently been an active field of research. A potential candidate for a pixel detector built in Silicon-On-Insulator (SOI) technology has already been characterized in terms of radiation hardness to TID (Total Ionizing Dose) and charge collection after a moderate neutron irradiation. In this article we present results of an extensive irradiation hardness study with neutrons up to a fluence of 1x10e16 neq/cm2. Charge collection in a passive pixelated structure was measured by Edge Transient Current Technique (E-TCT). The evolution of the effective space charge concentration was found to be compliant with the acceptor removal model, with the minimum of the space charge concentration being reached after 5x10e14 neq/cm2. An investigation of the in-pixel uniformity of the detector response revealed parasitic charge collection by the epitaxial silicon layer characteristic for the SOI design. The results were backed by a numerical simulation of charge collection in an equivalent detector layout.

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arXiv2017

Study of prototypes of LFoundry active and monolithic CMOS pixels sensors for the ATLAS detector

High Energy Particle Physics experiments at the LHC use hybrid silicon detectors, in both pixel and strip geometry, for their inner trackers. These detectors have proven to be very reliable and performant. Nevertheless, there is great interest in the development of depleted CMOS silicon detectors, which could achieve similar performances at lower cost of production and complexity. We present recent developments of this technology in the framework of the ATLAS CMOS demonstrator project. In particular, studies of two active sensors from LFoundry, CCPD_LF and LFCPIX, and the first fully monolithic prototype MONOPIX will be shown.

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arXiv2017

Depleted fully monolithic CMOS pixel detectors using a column based readout architecture for the ATLAS Inner Tracker upgrade

Depleted monolithic active pixel sensors (DMAPS), which exploit high voltage and/or high resistivity add-ons of modern CMOS technologies to achieve substantial depletion in the sensing volume, have proven to have high radiation tolerance towards the requirements of ATLAS in the high-luminosity LHC era. Depleted fully monolithic CMOS pixels with fast readout architectures are currently being developed as promising candidates for the outer pixel layers of the future ATLAS Inner Tracker, which will be installed during the phase II upgrade of ATLAS around year 2025. In this work, two DMAPS prototype designs, named LF-MonoPix and TJ-MonoPix, are presented. LF-MonoPix was designed and fabricated in the LFoundry 150~nm CMOS technology, and TJ-MonoPix has been designed in the TowerJazz 180~nm CMOS technology. Both chips employ the same readout architecture, i.e. the column drain architecture, whereas different sensor implementation concepts are pursued. The design of the two prototypes will be described. First measurement results for LF-MonoPix will also be shown.

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arXiv2017

Radiation hard pixel sensors using high-resistive wafers in a 150 nm CMOS processing line

Pixel sensors using 8" CMOS processing technology have been designed and characterized offering the benefits of industrial sensor fabrication, including large wafers, high throughput and yield, as well as low cost. The pixel sensors are produced using a 150 nm CMOS technology offered by LFoundry in Avezzano. The technology provides multiple metal and polysilicon layers, as well as metal-insulator-metal capacitors that can be employed for AC-coupling and redistribution layers. Several prototypes were fabricated and are characterized with minimum ionizing particles before and after irradiation to fluences up to 1.1 $\times$ 10$^{15}$ n$_{\rm eq}$ cm$^{-2}$. The CMOS-fabricated sensors perform equally well as standard pixel sensors in terms of noise and hit detection efficiency. AC-coupled sensors even reach 100% hit efficiency in a 3.2 GeV electron beam before irradiation.

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arXiv2016

Development of a Depleted Monolithic CMOS Sensor in a 150 nm CMOS Technology for the ATLAS Inner Tracker Upgrade

The recent R&D focus on CMOS sensors with charge collection in a depleted zone has opened new perspectives for CMOS sensors as fast and radiation hard pixel devices. These sensors, labelled as depleted CMOS sensors (DMAPS), have already shown promising performance as feasible candidates for the ATLAS Inner Tracker (ITk) upgrade, possibly replacing the current passive sensors. A further step to exploit the potential of DMAPS is to investigate the suitability of equipping the outer layers of the ATLAS ITk upgrade with fully monolithic CMOS sensors. This paper presents the development of a depleted monolithic CMOS pixel sensor designed in the LFoundry 150 nm CMOS technology, with the focus on design details and simulation results.

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arXiv2014

The RD53 Collaboration's SystemVerilog-UVM Simulation Framework and its General Applicability to Design of Advanced Pixel Readout Chips

The foreseen Phase 2 pixel upgrades at the LHC have very challenging requirements for the design of hybrid pixel readout chips. A versatile pixel simulation platform is as an essential development tool for the design, verification and optimization of both the system architecture and the pixel chip building blocks (Intellectual Properties, IPs). This work is focused on the implemented simulation and verification environment named VEPIX53, built using the SystemVerilog language and the Universal Verification Methodology (UVM) class library in the framework of the RD53 Collaboration. The environment supports pixel chips at different levels of description: its reusable components feature the generation of different classes of parameterized input hits to the pixel matrix, monitoring of pixel chip inputs and outputs, conformity checks between predicted and actual outputs and collection of statistics on system performance. The environment has been tested performing a study of shared architectures of the trigger latency buffering section of pixel chips. A fully shared architecture and a distributed one have been described at behavioral level and simulated; the resulting memory occupancy statistics and hit loss rates have subsequently been compared.

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arXiv2012

DEPFET active pixel detectors for a future linear $e^+e^-$ collider

The DEPFET collaboration develops highly granular, ultra-transparent active pixel detectors for high-performance vertex reconstruction at future collider experiments. The characterization of detector prototypes has proven that the key principle, the integration of a first amplification stage in a detector-grade sensor material, can provide a comfortable signal to noise ratio of over 40 for a sensor thickness of 50-75 $\mathrm{\mathbf{μm}}$. ASICs have been designed and produced to operate a DEPFET pixel detector with the required read-out speed. A complete detector concept is being developed, including solutions for mechanical support, cooling and services. In this paper the status of DEPFET R & D project is reviewed in the light of the requirements of the vertex detector at a future linear $\mathbf{e^+ e^-}$ collider.

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