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T. Nandha Kumar

Publications and source records attributed to T. Nandha Kumar.

3 recordsLinked to original sources

Solving Large Traveling Salesman Problems (TSPs) by a Recursive Clustering Algorithm and a Scalable FPGA-Based Implementation

The Traveling Salesman Problem (TSP) continues to attract significant research interest due to its critical role in various applications. This paper introduces a recursive clustering approach that divides cities into a limited number of clusters, each containing up to five cities and its own centroid. Constrained TSP and simulated annealing techniques are employed to route cities within each cluster, using the centroids of neighboring clusters as entry and exit points for the routing process. This method offers the benefit of producing accurate and cost-effective routing solutions, due to the reduced number of cities in each cluster. The connections between cluster centroids are established using simulated annealing. The FPGA-based proposed hardware implementation demonstrates the feasibility of routing a large number of cities, as the approach leverages memory to store cluster information. Consequently, the method is independent of the FPGA's logic hardware, and its scalability depends on the FPGA's memory capacity. Furthermore, distance calculations using approximate methods for the FPGA execution are compared and the squared Euclidean is chosen due to its low resources' utilization. Compared to previous methods, the proposed approach can handle more cities for routing, offering better scalability and a higher operating frequency.

cs.DC

Minimal Neuron Circuits: Bursters

This work introduces a novel methodology for designing biologically plausible bursting neuron circuits using a minimal number of components. We hypothesize that to design circuits capable of bursting, the neuron circuit design must mimic a neuron model that inherently exhibits bursting dynamics. Consequently, classical models such as the Hodgkin-Huxley, $I_{Na,p}+I_{K}$, and FitzHugh-Nagumo models are not suitable choices. Instead, we propose a methodology for designing neuron circuits that emulate the qualitative characteristics of the $I_{Na,p}+I_{K}+I_{K(M)}$ model, a well-established minimal bursting neuron model. Based on this methodology, we present two novel MOSFET-based circuits that exhibit bursting. Using the method of dissection of neural bursting, we demonstrate that the nullcline and bifurcation diagrams of the fast subsystem in our circuits are qualitatively equivalent to those of the $I_{Na,p}+I_{K}+I_{K(M)}$ model. Furthermore, we examine the effect of the type of bifurcation at burst initiation and termination on the bursting characteristics, showing that our circuits can exhibit diverse bursting behaviours. Importantly, the main contribution of this work lies not in the specific circuit implementation, but in the methodology proposed for constructing bursting neuron circuits.

cs.AR

Minimal Neuron Circuits -- Part I: Resonators

Spiking Neural Networks have earned increased recognition in recent years owing to their biological plausibility and event-driven computation. Spiking neurons are the fundamental building components of Spiking Neural Networks. Those neurons act as computational units that determine the decision to fire an action potential. This work presents a methodology to implement biologically plausible yet scalable spiking neurons in hardware. We show that it is more efficient to design neurons that mimic the $I_{Na,p}+I_{K}$ model rather than the more complicated Hodgkin-Huxley model. We demonstrate our methodology by presenting eleven novel minimal spiking neuron circuits in Parts I and II of the paper. We categorize the neuron circuits presented into two types: Resonators and Integrators. We discuss the methodology employed in designing neurons of the resonator type in Part I, while we discuss neurons of the integrator type in Part II. In part I, we postulate that Sodium channels exhibit type-N negative differential resistance. Consequently, we present three novel minimal neuron circuits that use type-N negative differential resistance circuits or devices as the Sodium channel. Nevertheless, the aim of the paper is not to present a set of minimal neuron circuits but rather the methodology utilized to construct those circuits.

cs.NE